Counting floating point for FSM design in Verilog

[aguntukbd]

Hi,
I am designing FSM for charging, discharging phases in inductor for AMS circuit. My counter works for integer numbers for different cycles. But in reality, it has to count floating point number or fractional numbers of fixed reference clock frequency depending on the different charging and discharging phases. How can I count upto a floating point number or fractional number? Should I use fixed point number in verilog? is there any simpler or efficient method? Your guideline or tips will be very useful!

PS: I am quite new to verilog & FSM design

 

[KlausST]

Hi,

The thing is the peak current of inductor will vary based on energy source and also different load values. So my switching time will be adjusted or better to say adapted. Therefore I have to make adaptive switching based on load and my inductor peak current and energy source. As I first had an idea of counting the value to zero for each phase (considering the integer value), my switching works by implementing counter by decrementing 1...

I guess everyone understood so far...

Now the problem is how to go on from here how can I count precision timing for fractional part?

The problem is your focussing on "fractional part".
The usual way is to do integer counts.

*****
Anyways. A counter needs
* a clock
* a counting direction
* a step size
(I gues you never defined any of them. We only know there is a 200MHz system clock)

The most often counters in digital desing are binary counters.
the have:
* a clock input
* a fixed direction or a direction input
* a step size of 1

Just assuming you manage to do floating point counting.
Still it will not have a benefit, because you can´t generate a "fractional step size PWM".

(Lets say you have 178$ available. You want to buy tires for your car. Each costs 55$. Yes, you can calculate that your money equals 3.236363 tires. Still you can buy only 3 of them)

****

Also you missed to define your PWM signal reagarding timing .. accuracy and precision.

Klaus

 

[aguntukbd]

Hi,

I guess everyone understood so far...


The problem is your focussing on "fractional part".
The usual way is to do integer counts.

*****
Anyways. A counter needs
* a clock
* a counting direction
* a step size
(I gues you never defined any of them. We only know there is a 200MHz system clock)

The most often counters in digital desing are binary counters.
the have:
* a clock input
* a fixed direction or a direction input
* a step size of 1

Just assuming you manage to do floating point counting.
Still it will not have a benefit, because you can´t generate a "fractional step size PWM".

(Lets say you have 178$ available. You want to buy tires for your car. Each costs 55$. Yes, you can calculate that your money equals 3.236363 tires. Still you can buy only 3 of them)

My fsm is working for integer count with 200 MHz clock and step size of 1. I simulated and it is working for integer phase values only. I defined the phase inputs as integer values and the fsm output switches are working as it should for the integer values (even with different integer values phases in different cycles)


But that is just preliminary implementation. Now in reality I have to deal with variable phases with fractions. I understand now I cannot go with counting. What other way I implement that if one of the phases is 13.725 * 200 MHz = 13.725 * 5ns, the corresponding output switch of fsm should open for that time only. Is the any other idea except counting in this case? or can I count till suppose 13 and then how to process till precise 0.725 times of the clock period?

Also you missed to define your PWM signal reagarding timing .. accuracy and precision.

Klaus

My PWM is adaptive. The corresponding switches of the 4 phases (which comes from the comparators of the block of output switch with capacitors) construct the timing of digital PWM. and the duration of phases change in each cycle (as load current, energy source voltage changing) which in turn changing the timing of the PWM in each cycle. The corresponding switches of the phases will be open for specific time which is given as input of the phases (one example is above 13.725 * 200 MHz = 13.725 * 5ns) in the fsm. Therefore that switch has to be open for this 13.725 * 5ns time. Therefore, the accuracy and precision depends on how accurately and precisely I keep the switch open for given phases for different cycles.

 

[kaz1]

My fsm is working for integer count with 200 MHz clock and step size of 1. I simulated and it is working for integer phase values only. I defined the phase inputs as integer values and the fsm output switches are working as it should for the integer values (even with different integer values phases in different cycles)


But that is just preliminary implementation. Now in reality I have to deal with variable phases with fractions. I understand now I cannot go with counting. What other way I implement that if one of the phases is 13.725 * 200 MHz = 13.725 * 5ns, the corresponding output switch of fsm should open for that time only. Is the any other idea except counting in this case? or can I count till suppose 13 and then how to process till precise 0.725 times of the clock period?

If your clock period is 5ns then that is your time resolution. To get around it try some fancy techniques such as both edges of clock or four clocks of 200Mhz at four phases then add logic to manage 5/4 ns. Otherwise I don't see it doable.

 

[ThisIsNotSam]

In the digital fully synchronous domain, your options are rather limited. You can think of a counter of positive edges and a counter of negative edges of clock, this gives you a slightly increased precision, but nowhere near the fractional amounts being discussed in here.

The use of posedge and negedge counters is the equivalent of changing the phase of clock by 180 degrees. With delays on the clock line, you can theoretically get multiple phases, nearly as many as you want. You can them sum the count of all the multiple phased counters and get higher precision. Controlling the phase with digital only logic is tricky though. You can do it with delay cells or inverters, but it is not perfect. You can also do a ring oscillator with a much higher frequency and count clock edges that way, but the oscillator will need calibration to withstand process variation.

Lots of options. All of them have drawbacks.

 

[kaz1]

My fsm is working for integer count with 200 MHz clock and step size of 1. I simulated and it is working for integer phase values only. I defined the phase inputs as integer values and the fsm output switches are working as it should for the integer values (even with different integer values phases in different cycles)

If your clock period is 5ns then that is your time resolution. To get around it try some fancy techniques such as both edges of clock or four clocks of 200Mhz at four phases then add logic to manage 5/4 ns. Otherwise I don't see it doable.

 

[barry]

You seem to be refusing to accept fundamental, and I mean FUNDAMENTAL principles. This discussion is going around in circles.

You can’t count periods of fractions of a clock. (You can count half-clocks if you use both edges, but that’s a degenerative case).

If you want to count, say, tenths of a clock, you’re going to need another clock which is ten times faster.

You might be able to do something using a bunch of delay lines, but my head hurts just thinking about that.

 

[aguntukbd]

Thanks a lot guys. I learned a lot and explored a lot of options. To measure frequency of such variables which changes also in each cycle is kind of impossible to implement in precise and even if it is close to possible the extra power that will add up for the circuit is unnecessary ...

I will go on implementing rounded up integer count in each cycle by toggling 1 integer count more or less in successive cycles. The error that will generate hopefully be compensated by delays if needed...

Thanks a lot

 

[KlausST]

To measure frequency

You want to measure frequency???

I always thought you wanted to generate the dutyCycle (t_on, t_off) for a PWM.

I´m confused.

Klaus

 

[dpaul]

You seem to be refusing to accept fundamental, and I mean FUNDAMENTAL principles. This discussion is going around in circles.

You can’t count periods of fractions of a clock. (You can count half-clocks if you use both edges, but that’s a degenerative case).

If you want to count, say, tenths of a clock, you’re going to need another clock which is ten times faster.

You might be able to do something using a bunch of delay lines, but my head hurts just thinking about that.

I gave up long ago on this post. Leave aside writing Verilog for a simple up/down counter or FSM design. The concept here itself seems to be confusing or not understood.