Counter cİrcuİt (3 forward 2 back)

[b]CODE VHDL[/b]

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;

ENTITY UP_3_DOWN_2 IS
	PORT(clk, rst : IN STD_LOGIC := '0';
			cnt : BUFFER INTEGER RANGE 0 TO 9 := 0);
END ENTITY UP_3_DOWN_2; 

ARCHITECTURE OP OF UP_3_DOWN_2 IS	
	
	SIGNAL cnt_int : INTEGER RANGE 0 TO 9 := 0;
	SIGNAL up	: STD_LOGIC := '1';
	
BEGIN
	
	process(clk, rst)
	begin
		if rst = '0' then 
			cnt <= 0;
			cnt_int <= 0;
			up <= '0';
		elsif clk = '1' and clk'event then
			cnt_int <= cnt_int + 1;
			if up = '1' then 
				if cnt_int = 2 then
					cnt_int <= 0;
					up <= '0';
				end if;
			else -- down
				 if cnt_int = 1 then
					 cnt_int <= 0;
					 up <= '1'; [B]-- FvM's correction[/B]
				 end if;
			end if;
			if up = '1' then
			  cnt <= cnt + 1;
		  else
			  cnt <= cnt - 1;
		  end if;
		end if;
	end process;
	
END ARCHITECTURE;