Converting Verilog to VHDL

[Akanimo]

The problem is that the code is big and I need to write VHDL for the whole code. I have done most of it but have some Verilog statements on which I have a doubt.
...

Yes, I understand that. I'm just considering how you can save time for waiting for reply.

For these short ones, you could just create two simple templates, one for Verilog and the other for VHDL. Your can cut and paste to create ports and body of codes in both, run synthesis and check the outcome. If they aren't the same, then you could ask here for the equivalent. I think that would save you some time.

 

[engr_joni_ee]

Hi,

I get an error on "bool_to_std_logic" function. I need to add the library but I guess it is fine if I use post #19 code instead of "bool_to_std_logic" function because it also compares two std_logic and assign std_logic to empty.

Here I have another problem. It is left shift and power. Any idea how to convert to VHDL ?

wr_ptr_gray_next = wr_ptr_next ^ (wr_ptr_next >> 1);

 

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^ is XOR not "power"
Also >> is RIGHT shift not LEFT shift. >> 1 means dropping the least significant bit, while shifting in a 0 at the most significant bit.

 

[engr_joni_ee]

This means that the equivalent VHDL of verilog statement in #22 is

wr_ptr_gray_next <= wr_ptr_next xor  ('0' & wr_ptr_next(GC_ADDR_WIDTH-1 downto 0));

where the signals are already defined as

signal wr_ptr_next      : std_logic_vector(GC_ADDR_WIDTH downto 0);  
signal wr_ptr_gray_next : std_logic_vector(GC_ADDR_WIDTH downto 0);

 

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Correct, that should be the equivalent VHDL version.

 

[vGoodtimes]

wr_ptr_gray_next <= wr_ptr_next xor ('0' & wr_ptr_next(wr_ptr_next'high downto wr_ptr_next'low+1));

VHDL also has an ASR operator but I don't recall what the issues were.

 

[engr_joni_ee]

Hi,

Another statement in Verilog which is bit strange.

assign mem_write_data = {s00_axis_tlast, s00_axis_tdata }; 
assign {m00_axis_tlast, m00_axis_tdata} = m00_data_reg;

where
m00_axis_tdata and s00_axis_tdata are 32 bit wide
m00_axis_tlast and s00_axis_tlast are 1 bit
m00_data_reg and mem_write_data are 34 bit wide

I don't understand how Verilog works in assign statements because there is a mismatch of 1 bit. The tdata is 32 and tlast is 1 bit which is assigned to 34 bit wide wire in Verilog and there is no error in compilation.

 

[FvM]

You would want to read Verilog LRM "10.7 Assignment extension and truncation". In Verilog, bit padding and truncation is performed in similar situations. VHDL in contrast requires exact matching of bit widths in assignments, you can e.g. use resize() or manual padding/truncation.

 

[wtr]

A google search would have helped you
But why do you want to? all tools allow mixed language.

I once worked at surrey satellites only to discover their license of modelsim did not allow multiple languages. You could either have only vcoms or vlibs, but heaven forbid you used both. It was probably some quirk associated to microsemi.

Anyway, your quote although true is also false.

 

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I once worked at surrey satellites only to discover their license of modelsim did not allow multiple languages. You could either have only vcoms or vlibs, but heaven forbid you used both. It was probably some quirk associated to microsemi.

Anyway, your quote although true is also false.

Don't you mean you could only use vcom or vlog to compile VHDL or Verilog?

Microsemi now ships with a version of Modelsim Pro that allows mixed simulations as they don't ship the tools with precompiled libraries for all the cores in both languages. Pretty much all tools now have default mixed support as IP cores come in one or the other and are seldom available in both.

Oh and it wasn't a quirk with Microsemi...Modeltech (and then Mentor) always made you pay twice for Modelsim, a license to support VHDL and a license to support Verilog. It's only been relatively recent that Mentor consolidated the licensing to default to mixed simulations. I think this was around the time they dropped SE and started pushing Questa.