shaiko
Advanced Member level 5
Sure.
Yet the only signal that requires CDC attention is the SCLK that's arriving to the slave. I.E, although this bus isn't synchronous to the FPGA system clock - it still has properties inherent to the protocol that we can exploit.
Yet the only signal that requires CDC attention is the SCLK that's arriving to the slave. I.E, although this bus isn't synchronous to the FPGA system clock - it still has properties inherent to the protocol that we can exploit.