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configurable wire from one module to another module in verilog

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tariq786

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Hi,

I want to know if there is a way in verilog to configure a wire from one module to another module such that during simulation, it exists as a regular wire for some simulation time and then as no wire for remaining simulation time. Here is what i mean


 

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  • configurable_wire_verilog.jpg
    configurable_wire_verilog.jpg
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You ask a lot of strange questions. How is the different from inserting a bufif0 primitive in the path if wire y?
 

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