configurable wire from one module to another module in verilog

tariq786 · Feb 6, 2013

Hi,

I want to know if there is a way in verilog to configure a wire from one module to another module such that during simulation, it exists as a regular wire for some simulation time and then as no wire for remaining simulation time. Here is what i mean

dave_59 · Feb 6, 2013

You ask a lot of strange questions. How is the different from inserting a bufif0 primitive in the path if wire y?

configurable wire from one module to another module in verilog

tariq786

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configurable wire from one module to another module in verilog

tariq786

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