Common methods for ensuring robustness to PVT

[analogLow]

Hello all!

Now that we have a few members, I am posing 2 questions to you all:
1. What process are you designing in?
2. How do you test for robustness to global and local variations?

Any other comments or recommended practices are encouraged here too.

cheers,
analogLow

 

[analogLow]

My answers:

1. I currently design in 65 nm CMOS.
2. Typically, at each global process corner, I run a Monte-Carlo simulation (i.e. local variations). Usually I use 50 runs or more. I have built chips with this method and had pretty ok luck. I have done analog and digital parts with this method.

Cheers,
analogLow