CMOS Switches in SC sigma-delta modulator

[borodenkov]

clock feedthrough offset sigma delta

I am designing SC multibit sigma-delta modulator in 0.18 CMOS and I have a problem with (most probably!) switches at the first integrator.

My design is differential 3rd order structure with one feedback path from 4-bit quantizer. The PSD of the modulator output has DC component and severe harmonic distortion (-45..-50dB), both even and odd ones.

The feedback from the quantizer is implemented as parallel 16 SC paths coming to the input of the OTA in the 1st integrator. I tried to change 3 of 4 switches in all these paths from CMOS gates to ideal switches (I had problems with conversion when changing all of them) and the performance of the modulator become close to the predicted one (SNR around 80db, no distortion). However when I change only some switches to ideal (e.g. the ones through which the input signal comes), the performance is again poor - harmonic distortion and DC offset.

Also I compared the performance of classical 2nd order structure with single bit and multibit quantizer - single bit works fine, but when I increase the number of bits, harmonic distortion appears and for 4 bits DC offset as well.

So I guess the problem is with the switches.. All real switches are CMOS transmission gates with minimal gate length. I chosed the NMOS and PMOS width so that the RC constant would be around 1/5 of the sampling half clock cycle. The ratio between PMOS and NMOS is around 5, so that the max Ron resistance is symmetrical from both NMOS and PMOS parts.

Can such a poor behavior be because of charge injection from switches? Or it comes from switch non-linearity (as I've written above I tried to back it as linear as possible)?

I would be very grateful if anyone could propose any hints for my problem.

Alex.

 

[uncle_urfi]

site:www.edaboard.com cmos switch

Clock Feedthrough can be minimized by choosing the ratio of pmos to nmos as L2=L1, W2=0.5W1. See page 422 of "Design of Analog Integrated Circuits" Razavi.

Using complementary switches can reduce charge injection at one level but cannot eliminate it completely. with many switches the distortion can continue to rise.

Try the following if it makes sense to you.

try to replace switches with ideal ones (one by one) and see when distortion reduces. It may be so that many switches are contributing to the problem or just one of them may be the culprit. since you know your circuit best, it would be wise to write down your observations in a journal and may be share with us when you have discovered something.

 

[uladz55]

If you use CMOS switch, to reduce feedthrough better to choose the same size of PMOS and NMOS transistors.
More accurate: Wp*Lp*Cox*(Vclk-Vsp-Vtp)=Wn*Ln*Cox*(Vclk-Vsn-Vtn),

W, L, Vt, Vs - size, threshold voltage, source voltage of MOST,
Vclk - clock signal applied to the gate of MOST.

regards,

Uladz55

 

[borodenkov]

Thanks for the ideas. In my case it apperared that:

1) Yes, charge injection from switches can be minimized choosing correctly W/L ratio for PMOS and NMOS in the CMOS switch (the ratio between PMOS and NMOS just slightly larger then 1). However this ratio makes the overall switch resistance more non-linear which causes lots of problems. So it is reasonable to linearize the switch as much as possible for signal-dependant path.

2) It is important to make the switches settling time non-dependant of input signal or comparator solution.

3) some 3rd order harm distorion (-80-100dB) still remains, so if high linearity is required, advanced techniques are necessary - bootstrapping or fixed Vgs overdrive circuits etc