CMOS Scaling on power

[Syukri]

cmos scaling theory

I've drawn a layout of differential Amp. using 018µ tech and 012µ foundry. The scaled factors S= 1.5 and U=1.667 in comparison of both the tech above.

By using General Scaling

P=1/U²

using 0.18µ power as referrence..

When i run simulation for 012 the error is almost 50 percent( P is calculated using above eqn )

Any idea why this happen and what should i do?

What is the right method to analyse and Analog cct?

 

[Yun Lin]

I don't know exactly you want to know.
But in general, when the design scales from other process, lots of parameter should be consider. Such as Vt, gate capacitance, not only the voltage and length.

 

[Syukri]

Yes I know..but according to the derivation using the equation only..all of it can be simplifie according to the relation to the scaling factors..

Well thanks for your answers..I think you suggest me to make it from strart.

 

[sunking]

for analog circuit, scaling theory is not fit.
Ever more, it need big device and large current in order to get the same performance for small process