D.A.(Tony)Stewart
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Hi,
I tried your method of making the sensor completely dark. I could see the effect in the camera picture. However they were not visible as shared in the picture but it was visible with close observations. Yes the sensor interface is LVDS. I tried changing the old layout by connecting a resistor between the bias pins. However that did not bring any change in the sensor picture. We use voltage regulators in the power supplies to supply the necessary digital voltage for the sensor.
Technical guy from the sensor company sent me an application note which discusses the column correction method. The document says that its due to the electrical non-uniformity in the row-drivers in the sensor architecture. The document suggests that I need to have a column corrector with correction co-efficients in the RAM of the FPGA. However I would like to solve the problem without using the FPGA resources. I do have an FPN corrector. However I doubt the FPN corrector can solve this column pattern problem. Any suggestions/views regarding it??
Your Attachment failed. Pls repost.
FPN typically corrects all pixel offsets and must be stored in ROM to correct each pixel for fixed pattern errors. Usually the problem is not gain related, but aging or offset drift is a problem, so recal, may be needed.
Not sure what 2 vertical lines look like. It this like the Sony thin conductor to dissipate static on CRT's? WHatever it is if it affects pixel gain, offset correction from FPN may not be adequate.
Spacial pixel filtering is employed for best results using FPGA running at pixel clock speeds.