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[SOLVED] CMOS Image Sensor effect

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Hi,

I tried your method of making the sensor completely dark. I could see the effect in the camera picture. However they were not visible as shared in the picture but it was visible with close observations. Yes the sensor interface is LVDS. I tried changing the old layout by connecting a resistor between the bias pins. However that did not bring any change in the sensor picture. We use voltage regulators in the power supplies to supply the necessary digital voltage for the sensor.

Technical guy from the sensor company sent me an application note which discusses the column correction method. The document says that its due to the electrical non-uniformity in the row-drivers in the sensor architecture. The document suggests that I need to have a column corrector with correction co-efficients in the RAM of the FPGA. However I would like to solve the problem without using the FPGA resources. I do have an FPN corrector. However I doubt the FPN corrector can solve this column pattern problem. Any suggestions/views regarding it??

Your Attachment failed. Pls repost.

FPN typically corrects all pixel offsets and must be stored in ROM to correct each pixel for fixed pattern errors. Usually the problem is not gain related, but aging or offset drift is a problem, so recal, may be needed.

Not sure what 2 vertical lines look like. It this like the Sony thin conductor to dissipate static on CRT's? WHatever it is if it affects pixel gain, offset correction from FPN may not be adequate.

Spacial pixel filtering is employed for best results using FPGA running at pixel clock speeds.
 

@Flote - Yes you are right, the manufacturer suggests to use a correction co-efficient to rectify the problem but I would like the sensor captured image to be homogeneous and perfect. I tried changing the bias registers which gives the analog voltages for the sensor to operate properly. I will try out your method and see if I see any changes.

@SunnySkyguy - which attachment are you talking about?? I have attached the image below.

**broken link removed**

As you can see the fine column like pattern in the image. The sensor manufacturer had sent me an application note which says that this pattern is due to the electrical non-uniformity of the sensor. It says in the app note

The pixels are controlled by signals from the side of the pixel array (row drivers etc.) and then read-out via column structures and multiplexed into a kernel with only a small number of channels. If the row drivers are non-uniform, this will cause a row-level pattern in the image that will be correctable using a set of coefficients containing only the
same number of elements as the number of rows.The most important nonuniformities originate in the analog sections of the readout stages, both on column level and kernel level and this document will a method of correcting these column level artifacts. Since the set of correction factors needed to correct the image on a column basis is only the length of a row (with one or two coefficients per element in the row), this typically enables the camera to store the correction coefficients in the FPGA only and no external memory needs to be used.
 

mmm I see, on my eyes the manufaturer should provide you an app note to make a correction of this columns without coefficients implementation in the FPGA. The solution that I proposed you is a very specific solution because ever CMOS sensor is different. And you have to check with tha manufacturer if that solution could be ok or not....
 

I contacted the sensor manufacturer and they said the sensor is still in evaluation phase, so different images obtained

Considering that exists a problem intrinsic to design of this product and the workaround of the 47K resistor did not work, it is clear that you must deal with an approach by an external software to the sensor. Once are you demanding an image accuracy superior to that the manufacturer can provide, the calibration by post processing seems to be the suitable decision, unless you change the sensor model.
 

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