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The best resources are documents and training materials from the foundries.
Which is foundry proprietary and confidential.
Meaning - you can see that only on the job, working for one of the companies using these technologies.
Nothing that is available in the open literature comes close, in my opinion, to the real life.
there is nothing special about a FinFET transistor. You have less flexibility than in older technologies. You will never draw a fin, for instance. It is always there, it is gridded and always present. You only have to align to it. You pretty much get 2 transistor templates from the foundry and you drop them into your layout. Things get a little messier when you get to the middle layers (M0), the connection rules are very wonky.
Yes, agreed, the layout still contains polygons.
But, if you look at the FinFET layout (devices with interconnects), you can tell immediately it is not a planar CMOS technology.
The style is completely different.
To the contrary, if you look at planar technology layout, it's hard to tell if that is 90nm, or 65nm, or 40nm.
Also, the amount of efforts required to make a clean and good (electrically) layout in FinFET nodes is much more than that for planar CMOS technology layouts.
If only doing real FinFET design layouts - with all their constraints, parasitics bottlenecks, complexity of multi-patterning, nonlinear effects, etc. etc. - would be that simple...
"I know karate, jiujitsu, sambo, judo, kungfu, and many other dangerous words"
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