Clock tree analysis and building

[devaVLSI]

why my clock tree is having more numbers of balancing cells? which is causing increase in latency.
Also how can i divide clk tree for analysis if the tree is having number of clk sources.

 

[navpics1]

u can check these items in ur design, that should give some pointers
1. is your clk skew target too aggressive ?
2. check whether your clock exceptions applied while building clk tree
3. conflicting balancing requirements at clk pins