Class A amplifier

[sze wen]

I need help to design a class A amplifier with 20dBm at 50 ohm of load at 4.5GHz.

How do I choose the right transistor sizing in Candence 180nm?

I take 0.6V as the input DC biasing voltage.
The Vdsat is 0.2V.

 

[BradtheRad]

Generally the high-side resistor can be about the same (up to 150% ohm value) as your load resistor. Tentatively you can than get the output at collector leg to hover around a range midway between your supply rails.

 

[sze wen]

Generally the high-side resistor can be about the same (up to 150% ohm value) as your load resistor. Tentatively you can than get the output at collector leg to hover around a range midway between your supply rails.

I am using MOSFET. The load should be inductive around 2.5nH. load from drain to ground is 50 ohm.

 

[D.A.(Tony)Stewart]

Using a -ve supply to create 20 dBm the amplifier needs to deliver a peak voltage swing of 3.16 V and a peak current of 63.2 mA into the 50-ohm load.

- Design for Id = 70 mA
- to maximize fT use the minimum channel length, L = 180nm
- choose a Vt= 2x Vdsat = 0.4V and Vgs-Vt = 0.2V
- thus I estimate W=46 μm should give us the desired current.
- gm = 17.6 mS, Cgs = 47.5 fF,
Use multi-finger gate paths to lower RC using 2.5 μm fingers use 20 fingers, giving W=50 μm and Id = 76 mA min using Vdd = 5V. You may choose a lower Vdd.
- ensure you have thermal vias below chip and wide traces to conduct heat away.

What do you get?

 

[sze wen]

How

Using a -ve supply to create 20 dBm the amplifier needs to deliver a peak voltage swing of 3.16 V and a peak current of 63.2 mA into the 50-ohm load.

- Design for Id = 70 mA
- to maximize fT use the minimum channel length, L = 180nm
- choose a Vt= 2x Vdsat = 0.4V and Vgs-Vt = 0.2V
- thus I estimate W=46 μm should give us the desired current.
- gm = 17.6 mS, Cgs = 47.5 fF,
Use multi-finger gate paths to lower RC using 2.5 μm fingers use 20 fingers, giving W=50 μm and Id = 76 mA min using Vdd = 5V. You may choose a lower Vdd.
- ensure you have thermal vias below chip and wide traces to conduct heat away.

What do you get?

How does W/L will give you the current needed?
The Cgs is the parasitic capacitance?
What happened to the inductor of 2.5nH?

 

[D.A.(Tony)Stewart]

How

How does W/L will give you the current needed?
The Cgs is the parasitic capacitance?
What happened to the inductor of 2.5nH?

If you studied FETs I should not have to tell you how to compute W/L , Cgs.

2.5 nH could be a 4 or 5mm trace and is 70 Ohms at 4.5 GHz for some reason.

 

[sze wen]

If you studied FETs I should not have to tell you how to compute W/L , Cgs.

2.5 nH could be a 4 or 5mm trace and is 70 Ohms at 4.5 GHz for some reason.

I couldn't get the UnCox.

 

[D.A.(Tony)Stewart]

The process design kit (PDK) manual for 180 nm ought to tell you that. Have you read it?

I believe in a 180nm CMOS process, μm for NMOS transistors typically ranges from 300 to 500 cm²/V·s

The gate oxide capacitance per unit area Cox=ϵox/tox
ϵox = ϵr⋅ϵ0 , ϵr= 3.9 approx.
tox = is typically around 4 to 4.5 nm thick

so correct me if I am wrong.

 

[sze wen]

The process design kit (PDK) manual for 180 nm ought to tell you that. Have you read it?

I believe in a 180nm CMOS process, μm for NMOS transistors typically ranges from 300 to 500 cm²/V·s

The gate oxide capacitance per unit area Cox=ϵox/tox
ϵox = ϵr⋅ϵ0 , ϵr= 3.9 approx.
tox = is typically around 4 to 4.5 nm thick

so correct me if I am wrong.

Sorry I did not read it. Thanks for letting me know.