cant understand this verilog code

[behzadmsl]

i have 1 module named A and 2 files with .v extension,named B and C.The point that should be considered is that B and C do not have any module-like definition,they just hold parameter values
//-----------------------------
`include "B.v"
`include "C.v"
module A (...);

endmodule
//-----------------------------

//------- B.v------------------
`ifndef _B_V_
`define _B_V_ 1

`define lgd 13
//-----------------------------

//------------ C.v-------------
parameters cop2 = 6'b010111;
.
.
.
//-----------------------------

I set A as my top-level ,and added files B and C to workspace, after compiling the outcome was depressing, it hadn't got parameters from these included files...what should i do to make it run?!!!!

 

[FvM]

Unlike defines, parameters are local to a module. That means, all parameters defined in module c.v will be ignored in your example, because the include statement is placed outside the module scope.

 

[behzadmsl]

also had done it,but didn't work