cant understand this verilog code

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behzadmsl

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hi,what does this code mean?? Why it's been defined this way??

output [0:0] mem_odt;
output [0:0] mem_cs_n;
output [0:0] mem_cke;
 

These are bit-vectors of length 1. They may be used in places, where a vector is expected, although you want to place only a single bit, e.g. in component instantiations.
 
thank u,Couldn't it be defined this way ??

output mem_odt ;
output mem_cs_n;
output mem_cke;
 

Both types aren't assigment compatible. You should check where mem_odt is used. You can have e.g. a component port ram_odt[0:NBIT-1]. In case of NBIT=1, the port is actually a single bit, but it's written as a vector. The vector [0:0] mem_odt can be connected to it, but a simple net can't.
 
I don't think Verilog cares. VHDL does distinguish between the two. That said, neither language has MATLAB's ability to treat anything as a multi-dimensional array.

Most likely, the 0:0 comes from a code translation or code generation script.
 
I don't think Verilog cares.
Click to expand...
Yes, you are right. I verified, that you can e.g. assign b[0] <= a[0:0] in Verilog code. The one bit length vector may be required in mixed language constructs, but I didn't try. Otherwise I agree with your explanation. Thanks for clarifying.
 

could u please clarify this module !! whats the meaning of having an `ifdef clause in module??


module de3 (

OSC1_50,

`ifdef TEST_BENCH
tm4_devbus,
`endif

`ifndef TEST_BENCH
,
JVC_CLK,
JVC_CS,
JVC_DATAOUT,
JVC_DATAIN
`endif
);

input OSC1_50;

`ifdef TEST_BENCH
inout [40:0] tm4_devbus;
`else
wire [40:0] tm4_devbus;

`ifndef TEST_BENCH
output JVC_CLK;
output JVC_CS;
output JVC_DATAOUT;
input JVC_DATAIN;
`endif
assign tm4_devbus={41{1'b1}};
`endif
 

The preprocessor commands are implementing conditional code evaluation, based on global switch variables. The code is completely different between testbench and other variant.
 

you mean if "TEST_BENCH" is valid then "inout [40:0] tm4_devbus;" port would be available and if it is not then we will have "wire [40:0] tm4_devbus;" and also a TEST_BENCH will be declared with these ports :"output JVC_CLK;","output JVC_CS;","output JVC_DATAOUT;"input JVC_DATAIN;" ???
 

Yes, this are two different components (with completely different port signals) in one. Not a typical example for reasonable usage of conditional evaluation in my opinion.
 
if we reckon de3 as a sub-module for module de2,and we make an instantiation of de3 in de2 module,then how we can initialize de3 !?? e.g we should have our instantiation like this

de3 de3_1(.TEST_BENCH(TEST_BENCH))

or we should do something else?!!
 

As you know you can make transistor level design in verilog,

here is the question,is it possible to implement this design on an FPGA ??
 

de3 de3_1(.TEST_BENCH(TEST_BENCH))
or we should do something else?!!
Click to expand...
the `ifdef construct is a pure text processing macro feature and doesn't interact with module ports or parameters. You have to use `define statements and `include definition files to get the intended effect.

As you know you can make transistor level design in verilog,
here is the question,is it possible to implement this design on an FPGA ??
Click to expand...
It's switch level modelling, not design. FPGAs have no programmable switches and can't synthesize transistor level logic. I don't think, that a synthesis tool will accept switch level descriptions and translate it to FPGA gate level representation, because it's beyond the purpose of a synthesis tool.
 
what is the difference between these two expressions :"pipereg #(1) pip1(...);" and "pipereg #1 pip2(...);"
Do both of them mean to have pip1 and pip2 after first cycle?!! or they are completely different???

module pipereg(....);
.
.
.
pipereg #(1) pip1(....);
pipereg #1 pip2(....);

endmodule;
 

They are the same. The #(1) just gives precedence to calculating the expression between ( ) brackets first, and after that's done it does the delay.

With (1) that's not super exciting, but IMO it is useful when you use macros or parameter expressions.

Arbitrary example....

Code: 
parameter t_reset = 100;
parameter some_scale = 1000;
parameter some_offset = 42;

pipereg #((t_reset*some_scale)+some_offset) pip1(...);

Does the exact same thing as:

Code: 
pipereg #100042 pip1(...);

This has nothing to do with number of cycles, it just waits for 100042 units of whatever the timescale is set to. With a default timescale of ns, that would be 100042 ns, i.e a little over 100 microseconds.
 
thank you,u r clarification was useful,would "pipereg #(x,y) pip3(...);" act the same way? will it make delay on x and y ?
 

Pipereg is a parameterized module. The #(1) construct sets the value of the parameter inside pipereg to 1 when it is instantiated. Not having seen the guts of pipereg, we don't know that the #(1) sets a delay. It might set the width of pipereg rather than the depth.

If pipereg has only one parameter to set, then typing #(x,y) will at best set the single parameter. More likely though, it will cause an error or warning when you synthesis or simulate.

r.b.
 
Last edited:
Doh! First drink coffee, then reply. Disregard what I said.

rberek is right, it's a parameterized module. It didn't register in the brain as such because ... 1) need coffee and 2) it's a better practice to use named parameters in stead of positional (like in your code).
 

rberek you were right,i have dozens of instantiations of pipereg in my code,which have different width of output ...thank you

and also coffee worked
 

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