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Hi,
In ADS 0.18 um TSMC process,
From my calculation I need to keep NMOS width around 350 um.
but getting restriction error that more than 100 um width not allowed.
What should I do to keep transistor width 350 um.
The drain current in MOSFET is directly proportional to width and inversely proportional to its channel length. So to have large drain current MOSFET width is kept larger than channel length. In a standard cell library there are different cells available for same function(e.g. NAND gate). They differs in their driving capability. Larger the width of transistor, higher the drain current so higher driving capability. But larger width causes larger gate capacitance which can cause larger slew at input. So depending on the requirement transistor width can be 2X,3X,4X of channel length.
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