calibrating analog multiplier

[garimella]

I have a circuit which does the operation A*B-C*D, where A,B,C,D are +/-10V signals. To perform this operation, iam using two analog multipliers (either AD633 or AD734 to be decided)
The accuracy required for output is around .05% of FSR. Now iam not quite sure as how to deal with inaccuracy of multiplier ICs, particularly in production lot. let us say A=5V, B=1V and C=5V and D=1V. The difference must be zero. But this will not happen because both multipliers are not matched with respect to accuracy and linearity. Suggestions required for workaround to deal with mismatch problem between multipliers.
btw: No scope of using micrcontrollers as this being part of a retrofit design module

 

[danadakk]

The first thing I see when I open 633 datasheet is :

Total error within 2% of full scale, non linearity +/-1%

So you want to do this with no processor.

So one has T & V & Offsets and Non linearity to correct. So a state machine, with memory (linearization table), ADC, Vref, analog muxing,
DAC, needed. One could consider a power curve or least squares fit to handle the non linearity problem. But that implies micro.

.05% is ~ 12 bit equivalent, and thats 12 bit after all error corrected in measurement/correction system. More
likely one would start with 16 bit A/D. And a DAC of equivalent error.....

Or one uses production cal approach :

Note DUT it shows as micro but can be just existing system modified to send its measurement
result and a EEPROM to receive correction values.

Or one uses a micro or FPGA with 16 bit or better DelSig (pick one with analog muxing, Vref, Gain, ....)

What is BW of signals ?

 

[KlausST]

Hi,

What you describe is not half of what is needed to give useful feedback.

A*B-C*D, where A,B,C,D are +/-10V signals

According this, the range of the result is +/-200V (FSR). I hope you agree this is not possible.
So what IS your output FSR?

The accuracy required for output is around .05% of FSR.

Obviously the ICs are not suitable for this. If you want 0.05% total error, then every single error needs to be smaller than this.

Initial errors, drift, noise ... and for sure all of inaccuracies of your own desgin (used resistors, thermocouple errors, added noise, power supply inaccuracies, settling time....
Internal errors may not be calibrated out by 100%.

In my eyes you should use ICs with better performance (don´t know whether they exist) or relax your requirements.

Klaus

 

[danadakk]

If BW signals low enough might be able to do this with 3 parts, mixed signal SOC, external Vref
(SOC good for +/- .1%), and DAC. Possible to use 16 bit PWM on SOC as the DAC......just 2 parts.
Is your .05% absolute accuracy or relative accuracy ?

Lots of alternatives, low chip count solutions........

 

[D.A.(Tony)Stewart]

I don't think I've ever seen a 10MHz analog multiplier better than 1%

You can try Dana's solution as simple Gilbert's won't cut it for temperature and supply drift.

https://tinyurl.com/24bcrloy

even with ideal Op Amps and matched transistors.

 

[crutschow]

this being part of a retrofit design module

Can't believe they achieved anywhere near that accuracy in the original design.