- Joined
- Jan 22, 2008
- Messages
- 53,049
- Helped
- 14,788
- Reputation
- 29,863
- Reaction score
- 14,275
- Trophy points
- 1,393
- Location
- Bochum, Germany
- Activity points
- 300,802
I see two points:
- generally, some additional losses may occur when changing the power stage operation mode to full PWM
- as I already mentioned, an explicite deadtime may be necessary. Because you are using a FPGA for control signal generation, an adjustable dead time can be easily provided.
- generally, some additional losses may occur when changing the power stage operation mode to full PWM
- as I already mentioned, an explicite deadtime may be necessary. Because you are using a FPGA for control signal generation, an adjustable dead time can be easily provided.