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FET in buck converter
It' difficult to judge the meaning of the shown waveform for high voltage operation without knowing the absolute commutated current. Also the actual dId/dt would be an interesting parameter.
Do I assume right, that the waveform has been acquired with the 10n/2R2 snubber in place. In this case, I get an commutating loop inductance of about 50 nH from the estimated resonace frequency. I think that a lower value should be achievable with TO220 transistor/diode and optimal layout.
On the other hand, the absolute voltage overshoot is proportional to circuit inductance and di/dt, not Ub. So it's not said, that it must be too high at nominal operation voltage.
From the -5V undershoot, which is apperently caused by the gate drive, I have some doubts about correct probe connection.
P.S.: Regarding saturation problem, with 0.44A*12 turn you get a H value of 75 A/m for the ungapped core, which means strong saturation. A few 10 µ airgap would avoid saturation, but also reduces the inductance to about 250 µH.
It' difficult to judge the meaning of the shown waveform for high voltage operation without knowing the absolute commutated current. Also the actual dId/dt would be an interesting parameter.
Do I assume right, that the waveform has been acquired with the 10n/2R2 snubber in place. In this case, I get an commutating loop inductance of about 50 nH from the estimated resonace frequency. I think that a lower value should be achievable with TO220 transistor/diode and optimal layout.
On the other hand, the absolute voltage overshoot is proportional to circuit inductance and di/dt, not Ub. So it's not said, that it must be too high at nominal operation voltage.
From the -5V undershoot, which is apperently caused by the gate drive, I have some doubts about correct probe connection.
P.S.: Regarding saturation problem, with 0.44A*12 turn you get a H value of 75 A/m for the ungapped core, which means strong saturation. A few 10 µ airgap would avoid saturation, but also reduces the inductance to about 250 µH.
