Bonding Diagram from Scratch for ASIC + Package?

[mahisdunya]

Hi everyone,
I am currently working on a university project where I need to design a bonding diagram for an ASIC that will be packaged using a JLCC68 (J-leaded ceramic chip carrier).
The ASIC has ~50 functional pads, and I’ve been given the pin descriptions by my supervisor, but no bonding diagram has been created yet. I now need to create one from scratch so the ASIC can be properly bonded and packaged.

-> My goal is to:

• Draw the die pad layout
• Map each pad to a JLCC68 package pin
• Create the wire bonding connections between the two
• Export it in a clean, correct format (PDF or CAD) for actual chip packaging

I have the JLCC68 datasheet and pad assignments. I understand the theory behind bonding diagrams, but I’m looking for practical, detailed guidance on:
1. What tools should I use to draw the bonding diagram? (Altium? Draw.io? Inkscape? Anything better? as it is a custom based ASIC so no layout or anything is available online as of yet.)
2. How to structure and align the die vs. package pads visually?
3. What format is standard for handing over bonding diagrams for packaging (PDF/DXF/etc.)?
4. Any tips or mistakes to avoid for a first-timer designing this for a real ASIC?
Any links, examples, screenshots, or templates would be really helpful!
Thanks in advance.

 

[dick_freebird]

I have done bond figures with IC layout tools, PowerPoint and pencil & ruler.

What does the assembly operation want to see?

Klayout can export GDSII and DXF, which would cover most I expect.

 

[mahisdunya]

Thanks a lot for your response!
At the moment, this is for a university project and the packaging might be handled manually or semi-manually.
I'm planning to create it using Draw.io or Inkscape and use pdf file.

Would that work or what would you recommend? Should i try Klayout now?

Appreciate your tips!

 

[dick_freebird]

If you have the GDSII mask art then a CAD program can be easiest. Chip is good to go (scaling consistency w/ package cavity drawing, known pad center cords, these also want to be right).

Where is your cavity drawing coming from?
I usually have to recapture from PDFs that the package vendor supplied, in the CAD tool that I'm using (open source or Brand X).

A "hand shop" will probably be more forgiving of discrepancies in numbers and sketch-y drawings. One that is all auto-bonders needs more correct and complete.

 

[mahisdunya]

Thanks again for the follow-up!
At the moment, I don’t have a GDSII or mask layout — the ASIC was designed by my supervisor and I was only provided with pin descriptions for now. I also don’t have a formal cavity drawing yet; I found a JLCC68 outline PDF online, which I’m planning to use for scaling and alignment.
Since this is likely going to a "hand shop" or done in-house for research, I’m hoping a precise PDF bonding diagram (with pin labels and die-to-package mapping) will be sufficient.