Bi-directional constant current device

[betwixt]

Here is an interesting challenge, I'm looking or ideas.

I've been asked to design a very low cost lighting device that uses voltage reversal to select which set of LED lights are illuminated when they are wired in two parallel chains of alternately reversed parallel LEDs. The chains will be driven with a 2KHz square wave with a short dead time at transitions and each chain will have about 500 LEDs, 250 wired one way and the other 250 wired in opposite polarity across the two wires. The maximum voltage allowed is +4V or -4V +/- 5% on one wire relative to the other. The chains might be shorter or longer depending on the end users chosen configuration but the current required has to be fixed at 300mA (600mA for both chains) from source. So essentially it is a voltage limited constant current but reversing polarity generator.

My first thought is a single constant current source supplying a H-Bridge with the four switches driven by an MCU. Given the low voltage it can be done without bootstrap supply. I wonder if any readers have alternative ideas. Cost is paramount. A single 12V unregulated supply is available.

Brian.

 

[wayne3]

Your file still shows the same odd combination of the two ramp circuits, which I still don't understand.

--- Updated Jan 28, 2025 ---

Okay, here's the circuit modified to provide a linear ramp and hold, up or down, using two separate control inputs to stop and hold the capacitor voltage at any desired value:
The V2 /Chg input goes low to charge the capacitor, and the V3 Dis input goes high to discharge the capacitor.
If V2 is high and V3 is low than the capacitor voltage (yellow trace) is held with no charge current in or out (45s to 50s, and 70s to 80s in the sim).

Is that what you want?

View attachment 197062

That‘s a good idea!
I re-examined my simulation files and got good results.
The purpose of the odd combination of two ramp circuits is to see if the voltages of the two ramp circuits can maintain the same difference between the rising and falling edges, but they can not.Why is this happening?

--- Updated Jan 28, 2025 ---

Certainly some asymmetries between current sink versus source :

View attachment 197051


Larger cap :

View attachment 197052

What does this mean? Can you give more explanation？
Are there some solutions？

 

[crutschow]

The purpose of the odd combination of two ramp circuits is to see if the voltages of the two ramp circuits can maintain the same difference between the rising and falling edges, but they can not.

I see no reason to do that.
What's the purpose of having the two ramps?
Why do you want the "same difference" between the two?

 

[wayne3]

I see no reason to do that.
What's the purpose of having the two ramps?
Why do you want the "same difference" between the two?

Haha, I'm just wondering about the difference between the two ramps.
To some extent, it can be summed up as a question of how capacitance affects the operation of a constant current source.

 

[danadakk]

That‘s a good idea!
I re-examined my simulation files and got good results.
The purpose of the odd combination of two ramp circuits is to see if the voltages of the two ramp circuits can maintain the same difference between the rising and falling edges, but they can not.Why is this happening?View attachment 197067View attachment 197068

--- Updated Jan 28, 2025 ---

What does this mean? Can you give more explanation？
Are there some solutions？

You have ramps that are not matched in their dV/dT rate, due to differences between
NPN and PNP and NPN-NPN PNP-PNP matching. The cap size smaller was simply to
get a triangle wave, eg. to prevent the current sources from running into their supply
rails and no longer function as linear V controlled current sources.

I may have missed it but what matching spec do you want for the source/sink current
generators ? And frequency range.....And I still dont understand hold specs.

 

[crutschow]

a question of how capacitance affects the operation of a constant current source.

An odd question.
It has no effect on (an ideal) current-source, only the rate at which the voltage changes on the capacitor.

 

[wayne3]

An odd question.
It has no effect on (an ideal) current-source, only the rate at which the voltage changes on the capacitor.

So, what you mean is, the problem is that the simulated current source is not the ideal current source, right?

--- Updated Jan 29, 2025 ---

You have ramps that are not matched in their dV/dT rate, due to differences between
NPN and PNP and NPN-NPN PNP-PNP matching. The cap size smaller was simply to
get a triangle wave, eg. to prevent the current sources from running into their supply
rails and no longer function as linear V controlled current sources.

I may have missed it but what matching spec do you want for the source/sink current
generators ? And frequency range.....And I still dont understand hold specs.

However, for the simulation, theoretically, both the NPN transistor and the PNP transistor can maintain the same characteristics, and the capacitance size is not within the setting range of the simulation.
The holding time is not important, I think the important thing is to ensure that the capacitor charge current is constant.
I would like to get a capacitor with a charge and discharge cycle of 10KHz.

 

[crutschow]

So, what you mean is, the problem is that the simulated current source is not the ideal current source, right?

Yes, transistors do not make a ideal current-source.
LTspice has an ideal current-source "current", if you want to use that.

I would like to get a capacitor with a charge and discharge cycle of 10KHz

What, exactly, is the purpose for doing that?

 

[wayne3]

Yes, transistors do not make a ideal current-source.
LTspice has an ideal current-source "current", if you want to use that.

What, exactly, is the purpose for doing that?

In simple terms, it is to convert the measurement time into the measurement voltage to reduce the ADC sampling requirements.

 

[crutschow]

In simple terms, it is to convert the measurement time into the measurement voltage to reduce the ADC sampling requirements.

Still no comprende.
What does a constant current-source have to do with an ADC voltage measurement?

 

[wayne3]

Still no comprende.
What does a constant current-source have to do with an ADC voltage measurement?

Sorry, I can't reveal too much.Thank you for your reply.