groover
Junior Member level 1
Sorry, no, I miswrote.
There will never be two modules that need to write the same bit at the same time (hence the merged A/B write), however one module may write it and another module may read it. This is in addition to read access via the "external" interface to my core.
There will never be two modules that need to write the same bit at the same time (hence the merged A/B write), however one module may write it and another module may read it. This is in addition to read access via the "external" interface to my core.