BDJ layout LVS problem

[hesam_ahmadi]

Hi all,
I draw layout of a Buried Double Junction(BDJ) Photo detector and create corresponding schematic too.
I've put two diode recognition layer in layout but when i do a LVS check, only one diode is recognized.

any suggestions about why only one diode is recognized?

BDJ cross section:


schematic:


Layout:


Thanks for your answers

 

[erikl]

May be because the nwell-substrate diode (your D1 nwpw) usually is extracted as a parasitic diode and so doesn't need a schematic counterpart for LVS.

 

[hesam_ahmadi]

May be because the nwell-substrate diode (your D1 nwpw) usually is extracted as a parasitic diode and so doesn't need a schematic counterpart for LVS.

Dear erikl, nwell-substrate diode isn't parasitic. it has schematic symbol and layout in the library.

 

[erikl]

Dear erikl, nwell-substrate diode isn't parasitic. it has schematic symbol and layout in the library.

Ok, this depends on the process used. Are you sure your nwpw D1 is an nwell-substrate diode, and not an nwell-pwell diode?

 

[hesam_ahmadi]

yes, i'm sure. it was written in process documents
i've tried different conditions and found that always the inner diode(P+/nwell) is recognized. if i remove the inner diode recognition layer, then the outer diode (nwell/sub) will be recognized.

 

[erikl]

From the outer diode (nwell/sub) recognition layer try to cut-out the area of the inner diode (P+/nwell) recognition layer -- so that the 2 recognition layers don't cover each other. Just a trial, though ...

 

[hesam_ahmadi]

Thanks erikl,
It works and now two photo diodes are detected. but there is another problem that i will report it here

 

[hesam_ahmadi]

Hi all,
This is the last problem about BDJ LVS checking.
The problem is that an extra net, named 4 ,is detected in layout. when i hilight it, it seems that it is on the same place as IN2 net.(see figure below)

 

[erikl]

Seems your extractor extracts the diodes separately from the electrical conducting layers (n-well & substrate), so I guess the corresponding connectivity rules are missing in your extract rules file. You must tell it -- somehow -- that in2 is identical to node 4 (its n-well), and in1 is identical to substrate.

If you can't change the extract rules file, you only can manipulate (cheat) the extracted netlist -- not a big problem for a single photo cell, but might get awesome, tedious and error-prone for a big array.

 

[israel_Y]

Helloo

I see you are working BDJ. I am working on a similar subject, my question is how do u simulate the response of the BDJ in software (is there anyway to simulate that using cadence? or any other software)..

I really appreciate any idea you can offer

Thanx

 

[erikl]

You must either calculate or measure the light responses of the 2 diodes, see this example:


The calculation of such a response is relatively complicated, as it depends on quite a lot of physical and geometrical properties of the diodes, like doping concentrations, junction depths, as well as layer properties like their thicknesses, wavelength dependent absorption constants and reflectivities.

Read this review paper for further info: A Review of the CMOS Buried Double Junction (BDJ) Photodetector and its Applications

 

[hesam_ahmadi]

Dear Israel_Y
If you mean BDJ light responses, You can use this SILVACO - Products - Luminous but if you want to simulate a BDJ in a specific technology, the only accurate way is measurement

 

[israel_Y]

Dear Israel_Y
If you mean BDJ light responses, You can use this SILVACO - Products - Luminous but if you want to simulate a BDJ in a specific technology, the only accurate way is measurement

if i have to do measurement, means i have to fabricate it rite?? but i cant afford to fabricate just for measurement (time and cost wise), so i am trying to "design" the most optimized BDJ for my application.

 

[hesam_ahmadi]

if i have to do measurement, means i have to fabricate it rite??.

Yes, that's write.
As i mentioned before, Luminous is a good tools to simulate a sample BDJ but due to lack of information about process parameters you can't simulate your BDJ designed in a specific process (for example a BDJ in TSMC 0.18 CMOS process)