Basys2 + 3bit counter

[cralx2k]

I need your help. I need to do 3 bit counter only in 3 7seg display. (000, 001, 010.......111...000)....
I’m having a hard time to figure out how I will assign all the led segments.
How about Q0, Q1, Q2, clkout1, clkout2?
Thanks all

module top(
input clk,
output enable_D1,
output enable_D2,
output enable_D3,
output enable_D4,
output ca,
output cb,
output cc,
output cd,
output ce,
output cf,
output cg,
output dp
);

wire clk5Mhz;
wire clkout1; // 152.587890625Hz
wire clkout2; // 76.2939453125Hz
wire clkOut; //
wire Q0,Q1,Q2; //


clk_gen UclkGen (
.CLKIN_IN(clk),
.CLKFX_OUT(clk5Mhz),
.CLKIN_IBUFG_OUT(),
.CLK0_OUT(),
.LOCKED_OUT()
);

clkDiv UclkDiv (
.clk(clk5Mhz),
.clkout1(clkout1),
.clkout2(clkout2),
.clkOut(clkOut)
);

counter Ucounter (
.clk(clkOut),
.Q0(Q0),
.Q1(Q1),
.Q2(Q2)
);


// place your code here!

reg [3:0] min_msb;
reg [3:0] min_lsb;
reg [3:0] sec_msb;
reg [3:0] sec_lsb;
reg out_disp;

//4x1 mux to display each of these based on the enable output.

always@(*) begin
case({enable_D1,enable_D2,enable_D3,enable_D4})
4'b0111: out_disp = min_msb;
4'b1011: out_disp = min_lsb;
4'b1101: out_disp = sec_msb;
4'b1111: out_disp = sec_lsb;
endcase
end

//Then have a 7 seg module connected to the out_disp signal.

endmodule

**broken link removed**