sureshaa
Member level 1
Hi all,
Basic edge triggered D flip flop: In an edge when the tsu and thold meets, it will latch the input to output.
Master slave D flip flop:In one rising (or falling) edge when the tsu and thold meets, it will latch the input to output in next rising edge (or falling).
1. My doubt is why FPGAs are using Master slave DFF ?
2. How to design a edge triggered D flip flop using any HDL?
3. Which one is faster either edge triggered Dff or D latch (By propagation delay or performance) ?
Correct me if i am wrong. Thanks in advance.
Basic edge triggered D flip flop: In an edge when the tsu and thold meets, it will latch the input to output.
Master slave D flip flop:In one rising (or falling) edge when the tsu and thold meets, it will latch the input to output in next rising edge (or falling).
1. My doubt is why FPGAs are using Master slave DFF ?
2. How to design a edge triggered D flip flop using any HDL?
3. Which one is faster either edge triggered Dff or D latch (By propagation delay or performance) ?
Correct me if i am wrong. Thanks in advance.