AXI master and slave with different clocks

[sun_ray]

I don't think that this RTL is free)) You can buy it(crypted) or write yourself, or try to search in web)


Yes. As I already said(twice by the way), master and slave clocks are defined by you, not the protocol version))

Should I take then that I can provide independent different clocks rto the AXI master and corresponding AXI slave irrespective of whether the master and slave follow AXI3, AXI4 (protocol version)?

Can you please let me know the connections of the pins of the async FIFO as asked in the last post?

Regards

 

[ivb1991]

Should I take then that I can provide independent different clocks rto the AXI master and corresponding AXI slave irrespective of whether the master and slave follow AXI3, AXI4 (protocol version)?

Can you please let me know the connections of the pins of the async FIFO as asked in the last post?

Regards

The answer to the first question is Yes.

I didn't understand clearly the second question. The AXI2AXI bridge has two interfaces - slave interface(SI) and master interface(MI). SI of the bridge must be connected to your master, and MI of the bridge must be connected to your slave.

 

[ads-ee]

Perhaps presented in a slightly different fashion...



the AXI master can be running on a different clock than the AXI slave. The AXI bridge [AXI slave-AXI master] will be running on both clocks and will have FIFOs between the two interfaces.

The AXI master device can be running at some multiple of the first AXI ACLK on axi_bus1 and the slave could be running at some multiple of the second AXI ACLK on axi_bus2.

 

[imbichie]

I think "single" in this case means "not differential".

Here single means nothing but same clock for Master and Slave.
The clock can be differential also.
In AMBA® AXI Protocol v1.0 Specification (AXI3), its not mentioned anything about the asynchronous AXI bridge.

 

[ivb1991]

Here single means nothing but same clock for Master and Slave.
The clock can be differential also.
In AMBA® AXI Protocol v1.0 Specification (AXI3), its not mentioned anything about the asynchronous AXI bridge.

1. Now I think that "single" means that master interface uses ONE clock signal, and slave interface uses ONE clock signal, but this clocks can be different. In spec there is no phrase about that master and slave must always operate at same clock signal.
2. If it's not mentioned anything about bridge, it doesn't mean that bridge cannot be implemented for AXI Protocol v1.0. The nice picture posted by ads-ee above is valid for any AXI protocol version.

 

[imbichie]

The nice picture posted by ads-ee above is valid for any AXI protocol version.

Yes its true, what i meant was in AMBA® AXI Protocol v1.0 Specification (AXI3), its not specified anything about the asynchronous bridge or different clocks for Master and Slave.

Now its clear that by designing such asynchronous bridge will make the Master and Slave operates at different clock

 

[sun_ray]

The answer to the first question is Yes.
ivb1991

I didn't understand clearly the second question. The AXI2AXI bridge has two interfaces - slave interface(SI) and master interface(MI). SI of the bridge must be connected to your master, and MI of the bridge must be connected to your slave.

The AXI2AXI bridge consists of 5 FIFO and each FIFO for each of the 5 AXI channels. My second question was how a FIFO will be connected with one channel.
For example let us take the address read channel of the AXI. Where will the data_in, wr_en, data_out, rd_en ports of the FIFO be connected? With which ports of the FIFO the ARLEN, ARID signals of the AXI master be connected?

Regards