AXI arvalid signal issue

Code Verilog - [expand]
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`define LOOPBACK 1
 
module read_instructions(clk, reset,
            i_axi_awready, o_axi_awid, o_axi_awaddr, o_axi_awlen, o_axi_awsize, o_axi_awburst,
            o_axi_awlock, o_axi_awcache, o_axi_awprot, o_axi_awqos, o_axi_awvalid,
            i_axi_wready, o_axi_wdata, o_axi_wstrb, o_axi_wlast, o_axi_wvalid,
            i_axi_bid, i_axi_bresp, i_axi_bvalid, o_axi_bready, 
            i_axi_arready, o_axi_arid, o_axi_araddr, o_axi_arlen, o_axi_arsize, o_axi_arburst,
            o_axi_arlock, o_axi_arcache, o_axi_arprot, o_axi_arqos, o_axi_arvalid,
            i_axi_rid, i_axi_rresp, i_axi_rvalid, i_axi_rdata, i_axi_rlast, o_axi_rready);
 
 
 
 
`ifdef FORMAL
    // AXI Address width (log wordsize) for DDR
    parameter C_AXI_ADDR_WIDTH = 9; // just for random test, need to change for actual neural network
    parameter C_AXI_DATA_WIDTH = 8; // related to AxSIZE
    parameter C_SIZE_OF_CACHE = 4; // for storing weights and biases parameters of neural network
`else
    // AXI Address width (log wordsize) for DDR
    parameter C_AXI_ADDR_WIDTH = 12; // just for random test, need to change for actual neural network
    parameter C_AXI_DATA_WIDTH = 128; // related to AxSIZE
    parameter C_SIZE_OF_CACHE = 64; // for storing weights and biases parameters of neural network
`endif
 
parameter C_AXI_ID_WIDTH    =   1;
 
localparam NUM_OF_BITS_PER_BYTES = 8;
localparam INCR_BURST_TYPE = 2'b01; // AxBURST[2:0] , see 'burst type' section in AXI spec
 
// AXI4 extends burst length support for the INCR burst type to 1 to 256 transfers. 
// Support for all other burst types in AXI4 remains at 1 to 16 transfers.
// for wrapping bursts, the burst length must be 2, 4, 8, or 16
// a burst must not cross a 4KB address boundary
// early termination of bursts is not supported
localparam MAX_BURST_LENGTH = 255; 
 
localparam BURST_SIZE_ENCODING_WIDTH = 3; // AxSIZE[2:0] , see 'burst size' section in AXI spec
localparam SUBWORD_SMALLEST_UNIT = 8; // smallest granularity in AXI protocol : 8 bit
localparam PROT_BITWIDTH = 3;
localparam QOS_BITWIDTH = 4;
localparam CACHE_BITWIDTH = 4;
 
 
input clk, reset;
 
// AXI write address channel signals
    input   wire            i_axi_awready; // Slave is ready to accept
    output  wire    [C_AXI_ID_WIDTH-1:0]    o_axi_awid; // Write ID
    output  reg [C_AXI_ADDR_WIDTH-1:0]  o_axi_awaddr;   // Write address
    output  wire    [$clog2(MAX_BURST_LENGTH)-1:0]      o_axi_awlen;    // Write Burst Length
    output  wire    [BURST_SIZE_ENCODING_WIDTH-1:0]     o_axi_awsize;   // Write Burst size
    output  wire    [1:0]       o_axi_awburst;  // Write Burst type
    output  wire    [0:0]       o_axi_awlock;   // Write lock type
    output  wire    [CACHE_BITWIDTH-1:0]        o_axi_awcache;  // Write Cache type
    output  wire    [PROT_BITWIDTH-1:0]     o_axi_awprot;   // Write Protection type
    output  wire    [QOS_BITWIDTH-1:0]      o_axi_awqos;    // Write Quality of Svc
    output  reg         o_axi_awvalid;  // Write address valid
 
// AXI write data channel signals
    input   wire            i_axi_wready;  // Write data ready
    output  reg [C_AXI_DATA_WIDTH-1:0]  o_axi_wdata;    // Write data
    output  reg [C_AXI_DATA_WIDTH/SUBWORD_SMALLEST_UNIT-1:0] o_axi_wstrb;   // Write strobes
    output  reg         o_axi_wlast;    // Last write transaction
    output  reg         o_axi_wvalid;   // Write valid
 
// AXI write response channel signals
/* verilator lint_off UNUSED */
    input wire [C_AXI_ID_WIDTH-1:0] i_axi_bid;  // Response ID
/* verilator lint_on UNUSED */
    input   wire [1:0]      i_axi_bresp;    // Write response
    input   wire            i_axi_bvalid;  // Write reponse valid
    output  wire            o_axi_bready;  // Response ready
 
// AXI read address channel signals
    input   wire            i_axi_arready;  // Read address ready
    output  wire    [C_AXI_ID_WIDTH-1:0]    o_axi_arid; // Read ID
    output  reg [C_AXI_ADDR_WIDTH-1:0]  o_axi_araddr;   // Read address
    output  wire    [$clog2(MAX_BURST_LENGTH)-1:0]      o_axi_arlen;    // Read Burst Length
    output  wire    [BURST_SIZE_ENCODING_WIDTH-1:0]     o_axi_arsize;   // Read Burst size
    output  wire    [1:0]       o_axi_arburst;  // Read Burst type
    output  wire    [0:0]       o_axi_arlock;   // Read lock type
    output  wire    [CACHE_BITWIDTH-1:0]        o_axi_arcache;  // Read Cache type
    output  wire    [PROT_BITWIDTH-1:0]     o_axi_arprot;   // Read Protection type
    output  wire    [QOS_BITWIDTH-1:0]      o_axi_arqos;    // Read Quality of Svc
    output  reg         o_axi_arvalid;  // Read address valid
 
/* verilator lint_off UNUSED */
// AXI read data channel signals
    input wire [C_AXI_ID_WIDTH-1:0] i_axi_rid;     // Response ID
/* verilator lint_on UNUSED */
    input   wire    [1:0]       i_axi_rresp;   // Read response
    input   wire            i_axi_rvalid;  // Read reponse valid
    input wire [C_AXI_DATA_WIDTH-1:0] i_axi_rdata;    // Read data
    input   wire            i_axi_rlast;    // Read last
    output  wire            o_axi_rready;  // Read Response ready
 
 
 
 
always @(posedge clk) 
begin
    if(reset) o_axi_wstrb <= 0;
 
    // burst alignment mechanism, see [url]https://i.imgur.com/jKbzfFo.png[/url]
    // o_axi_wstrb <= (~0) << (o_axi_awaddr % o_axi_awlen);
    // all the bracket variables are for removing verilator width warnings
 
    else o_axi_wstrb <= ((~0) << (o_axi_awaddr % 
                                  {{(C_AXI_ADDR_WIDTH-$clog2(MAX_BURST_LENGTH)){1'b0}}, o_axi_awlen}));
end
 
wire write_response_is_ok = i_axi_bvalid && ((i_axi_bresp == 'b00) || (i_axi_bresp == 'b01));
 
// need to implement data re-transmission
wire write_response_is_not_ok = i_axi_bvalid && !((i_axi_bresp == 'b00) || (i_axi_bresp == 'b01));
 
 
always @(posedge clk) 
begin
    if(reset) 
    begin 
        o_axi_wvalid <= 0;
    end
 
    else if(!(o_axi_wvalid && !i_axi_wready))
    begin
        // Note that both o_axi_awsize , o_axi_awlen are of hardware constants, so no multiply hardware
        // since this is for testing, WDATA just uses some values up to the total size of the write address space
        // Note: a master must not wait for AWREADY to be asserted before driving WVALID
        o_axi_wvalid <= (o_axi_wlast) ? 0 : 
                        (o_axi_wdata < (o_axi_awsize*o_axi_awlen)); 
    end
end
 
wire ddr_write_address_range_is_valid = (o_axi_awaddr < (1 << C_AXI_ADDR_WIDTH));
 
always @(posedge clk) 
begin   
    if(reset) o_axi_awvalid <= 0;
 
    // AXI specification: A3.3.1 Dependencies between channel handshake signal
    // the VALID signal of the AXI interface sending information must not be dependent on 
    // the READY signal of the AXI interface receiving that information
    // this is to prevent deadlock 
    // since AXI slave could wait for i_axi_awvalid to be true before setting o_axi_awready true.
    // Note: For same interface, VALID cannot depend upon READY, but READY can depends upon VALID
    // Note: Once VALID is asserted, it MUST be kept asserted until READY is asserted.
    //       VALID signal needs to be set (initially) independent of READY signal, 
    //       and then only ever adjusted if !(VALID && !READY)
    // Note: the master must not wait for the slave to assert AWREADY before asserting AWVALID
    // Note: (!(o_axi_awvalid && !i_axi_awready)) == (!awvalid || awready) 
    //       == (!awvalid || (awvalid && awready)). 
    //       it means "no transaction in progress or transaction accepted"
    else if(!(o_axi_awvalid && !i_axi_awready))
            o_axi_awvalid <= /*i_axi_awready &&*/ (ddr_write_address_range_is_valid);
end
 
wire write_transaction_is_accepted = (o_axi_wvalid) && (i_axi_wready);
wire address_write_transaction_is_accepted = (o_axi_awvalid) && (i_axi_awready);
 
always @(posedge clk)
begin
    if(reset) 
    begin
        o_axi_awaddr <= 0;
        //o_axi_wdata <= 0;
    end
 
    else if(address_write_transaction_is_accepted) 
    begin
        o_axi_awaddr <= o_axi_awaddr + 1;
        //o_axi_wdata <= o_axi_wdata + 1;
    end
end
 
always @(posedge clk)
begin
    if(reset) 
    begin
        //o_axi_awaddr <= 0;
        o_axi_wdata <= 0;
    end
 
    else if(write_transaction_is_accepted) 
    begin
        //o_axi_awaddr <= o_axi_awaddr + 1;
        o_axi_wdata <= o_axi_wdata + 1;
    end
end
 
`ifdef LOOPBACK
wire read_address_contains_loopback_data = 
(o_axi_awaddr > (o_axi_araddr + {{(C_AXI_ADDR_WIDTH-$clog2(MAX_BURST_LENGTH)){1'b0}}, o_axi_awlen}));
`endif
 
wire ddr_read_address_range_is_valid = (o_axi_araddr < (1 << C_AXI_ADDR_WIDTH));
 
 
always @(posedge clk) 
begin   
    if(reset) o_axi_arvalid <= 0;
 
    // AXI specification: A3.3.1 Dependencies between channel handshake signal
    // the VALID signal of the AXI interface sending information must not be dependent on 
    // the READY signal of the AXI interface receiving that information
    // this is to prevent deadlock 
    // since AXI slave could wait for i_axi_arvalid to be true before setting o_axi_arready true.
    // Note: For same interface, VALID cannot depend upon READY, but READY can depends upon VALID
    // Note: Once VALID is asserted, it MUST be kept asserted until READY is asserted.
    //       VALID signal needs to be set (initially) independent of READY signal, 
    //       and then only ever adjusted if !(VALID && !READY)
    // Note: the master must not wait for the slave to assert ARREADY before asserting ARVALID
    // Note: (!(o_axi_arvalid && !i_axi_arready)) == (!arvalid || arready) 
    //       == (!arvalid || (arvalid && arready)). 
    //       it means "no transaction in progress or transaction accepted"
    // Note: o_axi_rready is used for backpressure mechanism
    else if(!(o_axi_arvalid && !i_axi_arready))
        `ifdef LOOPBACK
            o_axi_arvalid <= /*i_axi_arready &&*/ (ddr_read_address_range_is_valid) && 
                            (read_address_contains_loopback_data) && 
                            (o_axi_bready && i_axi_bvalid && write_response_is_ok);
        `else
            o_axi_arvalid <= /*i_axi_arready &&*/ (ddr_read_address_range_is_valid);
        `endif
end
 
 
reg [$clog2(MAX_BURST_LENGTH)-1:0] num_of_write_transactions;
 
always @(posedge clk) 
begin   
    if(reset) num_of_write_transactions <= 0;
 
    else if(o_axi_wvalid && i_axi_wready)
            num_of_write_transactions <= (o_axi_wlast) ? 0 : num_of_write_transactions + 1;
end
 
always @(posedge clk) 
begin   
    if(reset) o_axi_wlast <= 0;
 
    else o_axi_wlast <= (num_of_write_transactions == (o_axi_awlen - 1));
end
 
 
//assign o_axi_wlast = 0;
assign o_axi_awid = 0;
assign o_axi_awlen = 15; // each burst has (Burst_Length = AxLEN[7:0] + 1) data transfers
 
/* verilator lint_off WIDTH */
assign o_axi_awsize = $clog2(C_AXI_DATA_WIDTH/NUM_OF_BITS_PER_BYTES); // 128 bits (16 bytes) of data when AxSIZE[2:0] = 3'b100
// Burst_Length = AxLEN[7:0] + 1, to accommodate the extended burst length of the INCR burst type in AXI4.
/* verilator lint_on WIDTH */
 
assign o_axi_awburst = INCR_BURST_TYPE;
assign o_axi_awlock = 0;
assign o_axi_awcache = 0;
assign o_axi_awprot = 0;
assign o_axi_awqos = 0; // no priority or QoS concept
 
 
 
assign o_axi_arqos = 0; // no priority or QoS concept
assign o_axi_arburst = INCR_BURST_TYPE;
 
/* verilator lint_off WIDTH */
assign o_axi_arsize = $clog2(C_AXI_DATA_WIDTH/NUM_OF_BITS_PER_BYTES); // 128 bits (16 bytes) of data when AxSIZE[2:0] = 3'b100
// Burst_Length = AxLEN[7:0] + 1, to accommodate the extended burst length of the INCR burst type in AXI4.
/* verilator lint_on WIDTH */
 
assign o_axi_arlen = 15; // each burst has (Burst_Length = AxLEN[7:0] + 1) data transfers
assign o_axi_arprot = 3'b010; // {data access, non-secure access, unprivileged access}
assign o_axi_arlock = 0; // AXI4 does not support locked transactions. 
assign o_axi_arcache = 0; // mostly used for HPS (hard processor system) such as ARM hard CPU IP
 
assign o_axi_arid = 0; // there is one AXI slave which is the DDR memory (A, B, or C) ?
 
// what situations will render data requester (AXI master) busy to receive read response ??
// such as AXI interconnect where arbitration will fail to acquire the data transfer priority
// such as the internal cache storage to store the data from external DDR memory is now full
// So, let's use a random value that is $anyseq in formal verification
assign o_axi_rready = (reset) ? 1 : `ifdef FORMAL $anyseq `else (!cache_is_full) `endif; 
 
// The master can assert BREADY before BVALID is asserted.
assign o_axi_bready = (reset) ? 1 : `ifdef FORMAL $anyseq `else (i_axi_bvalid) `endif; 
 
wire address_read_transaction_is_accepted = (o_axi_arvalid) && (i_axi_arready);
 
always @(posedge clk)
begin
    if(reset) o_axi_araddr <= 0;
 
    // When ARVALID & ARREADY are both high the next ARADDR can be generated 
    // because the current address for the current transfer is now complete (ARVALID & ARREADY).
    else if(address_read_transaction_is_accepted) 
        o_axi_araddr <= o_axi_araddr + 1; // increments DDR address to read instructions from
end
 
 
/* verilator lint_off UNUSED */
wire arm_write_param_enable;
wire [C_AXI_DATA_WIDTH-1:0] arm_write_param_data;
 
wire cache_is_empty;
 
wire [$clog2(C_SIZE_OF_CACHE)-1:0] cache_address_for_reading;
assign cache_address_for_reading = 0; // for testing only
/* verilator lint_on UNUSED */
 
 
wire valid_read_response_does_not_contain_error_messages = i_axi_rvalid && (i_axi_rresp == 0);
 
wire cache_is_full; // needed since C_SIZE_OF_CACHE is always smaller than SIZE_OF_DDR_MEMORY
 
 
// for storing neural network parameters (weights and biases) at destination side, 
// so this bram acts as intermediate cache (much smaller size than DDR memory) for the neural network
// no need AXI protocol in order to save logic usage, thus lesser area and power consumption
cache_controller #(.C_DATA_WIDTH(C_AXI_DATA_WIDTH), .C_SIZE_OF_CACHE(C_SIZE_OF_CACHE)) nn_feature_cache 
(
    .clk(clk), .reset(reset),
    .i_data(i_axi_rdata), // NN params coming from DDR memory
    .i_data_is_valid
     ((o_axi_rready && valid_read_response_does_not_contain_error_messages)), // DDR data is valid
    .i_addr(cache_address_for_reading),
    .full(cache_is_full), // NN params cache is full
    .o_data(arm_write_param_data), // NN params going to neural network layers
    .o_data_is_valid(arm_write_param_enable), // neural network layers to start another intermediate computations
    .empty(cache_is_empty) // no NN params to feed into the neural network layers
);
 
`ifdef FORMAL
 
localparam SIXTH_ADDRESS_IN_REQUEST = 6;
 
initial assume(reset);
 
reg first_clock_had_passed = 0;
 
always @(posedge clk) first_clock_had_passed <= 1;
 
always @(posedge clk) 
    if(first_clock_had_passed) 
        cover((o_axi_araddr > SIXTH_ADDRESS_IN_REQUEST) && address_read_transaction_is_accepted &&
                $past(i_axi_arready) && $past(o_axi_rready) && !o_axi_rready);
 
`endif
 
endmodule

Code Verilog - [expand]
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bram_axi_controller #(.C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH)) ddr_nn_params
(
    .clk(clk), .reset(reset),
    .o_axi_awready(axi_awready[0]), .i_axi_awid(axi_awid[0]),       .i_axi_awaddr(axi_awaddr[0]), 
    .i_axi_awlen(axi_awlen[0]),     .i_axi_awsize(axi_awsize[0]),   .i_axi_awburst(axi_awburst[0]),
    .i_axi_awlock(axi_awlock[0]),   .i_axi_awcache(axi_awcache[0]), .i_axi_awprot(axi_awprot[0]), 
    .i_axi_awqos(axi_awqos[0]),     .i_axi_awvalid(axi_awvalid[0]), .o_axi_wready(axi_wready[0]), 
    .i_axi_wdata(axi_wdata[0]),     .i_axi_wstrb(axi_wstrb[0]),     .i_axi_wlast(axi_wlast[0]), 
    .i_axi_wvalid(axi_wvalid[0]),   .o_axi_bid(axi_bid[0]),         .o_axi_bresp(axi_bresp[0]), 
    .o_axi_bvalid(axi_bvalid[0]),   .i_axi_bready(axi_bready[0]),   .o_axi_arready(axi_arready[0]), 
    .i_axi_arid(axi_arid[0]),       .i_axi_araddr(axi_araddr[0]),   .i_axi_arlen(axi_arlen[0]), 
    .i_axi_arsize(axi_arsize[0]),   .i_axi_arburst(axi_arburst[0]), .i_axi_arlock(axi_arlock[0]), 
    .i_axi_arcache(axi_arcache[0]), .i_axi_arprot(axi_arprot[0]),   .i_axi_arqos(axi_arqos[0]), 
    .i_axi_arvalid(axi_arvalid[0]), .o_axi_rid(axi_rid[0]),         .o_axi_rresp(axi_rresp[0]), 
    .o_axi_rvalid(axi_rvalid[0]),   .o_axi_rdata(axi_rdata[0]),     .o_axi_rlast(axi_rlast[0]), 
    .i_axi_rready(axi_rready[0])
);

Code VHDL - [expand]
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-------------------------------------------------------------------------------
-- SRL_FIFO entity and architecture
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- **                                                                     **
-- ** DISCLAIMER OF LIABILITY                                             **
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-- ** grants you a license to use this text/file solely for               **
-- ** design, simulation, implementation and creation of                  **
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-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        srl_fifo.vhd
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              srl_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.1.4.1 $
-- Date:            $Date: 2010/09/14 22:35:47 $
--
-- History:
--   goran  2001-05-11    First Version
--   KC     2001-06-20    Added Addr as an output port, for use as an occupancy
--                        value
--
--   DCW    2002-03-12    Structural implementation of synchronous reset for
--                        Data_Exists DFF (using FDR)
--   jam    2002-04-12    added C_XON generic for mixed vhdl/verilog sims
--
--   als    2002-04-18    added default for XON generic in SRL16E, FDRE, and FDR
--                        component declarations
--
--     DET     1/17/2008     v4_00_a
-- ~~~~~~
--     - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
 
entity SRL_FIFO is
  generic (
    C_DATA_BITS : natural := 8;
    C_DEPTH     : natural := 16;
    C_XON       : boolean := false
    );
  port (
    Clk         : in  std_logic;
    Reset       : in  std_logic;
    FIFO_Write  : in  std_logic;
    Data_In     : in  std_logic_vector(0 to C_DATA_BITS-1);
    FIFO_Read   : in  std_logic;
    Data_Out    : out std_logic_vector(0 to C_DATA_BITS-1);
    FIFO_Full   : out std_logic;
    Data_Exists : out std_logic;
    Addr        : out std_logic_vector(0 to 3) -- Added Addr as a port
    );
 
end entity SRL_FIFO;
 
architecture IMP of SRL_FIFO is
 
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
 
  component SRL16E is
      -- pragma translate_off
    generic (
      INIT : bit_vector := X"0000"
      );
      -- pragma translate_on    
    port (
      CE  : in  std_logic;
      D   : in  std_logic;
      Clk : in  std_logic;
      A0  : in  std_logic;
      A1  : in  std_logic;
      A2  : in  std_logic;
      A3  : in  std_logic;
      Q   : out std_logic);
  end component SRL16E;
 
  component LUT4
    generic(
      INIT : bit_vector := X"0000"
      );
    port (
      O  : out std_logic;
      I0 : in  std_logic;
      I1 : in  std_logic;
      I2 : in  std_logic;
      I3 : in  std_logic);
  end component;
 
  component MULT_AND
    port (
      I0 : in  std_logic;
      I1 : in  std_logic;
      LO : out std_logic);
  end component;
 
  component MUXCY_L
    port (
      DI : in  std_logic;
      CI : in  std_logic;
      S  : in  std_logic;
      LO : out std_logic);
  end component;
 
  component XORCY
    port (
      LI : in  std_logic;
      CI : in  std_logic;
      O  : out std_logic);
  end component;
 
  component FDRE is
    port (
      Q  : out std_logic;
      C  : in  std_logic;
      CE : in  std_logic;
      D  : in  std_logic;
      R  : in  std_logic);
  end component FDRE;
 
  component FDR is
    port (
      Q  : out std_logic;
      C  : in  std_logic;
      D  : in  std_logic;
      R  : in  std_logic);
  end component FDR;
 
  signal addr_i       : std_logic_vector(0 to 3);  
  signal buffer_Full  : std_logic;
  signal buffer_Empty : std_logic;
 
  signal next_Data_Exists : std_logic;
  signal data_Exists_I    : std_logic;
 
  signal valid_Write : std_logic;
 
  signal hsum_A  : std_logic_vector(0 to 3);
  signal sum_A   : std_logic_vector(0 to 3);
  signal addr_cy : std_logic_vector(0 to 4);
  
begin  -- architecture IMP
 
  buffer_Full <= '1' when (addr_i = "1111") else '0';
  FIFO_Full   <= buffer_Full;
 
  buffer_Empty <= '1' when (addr_i = "0000") else '0';
 
  next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
                      (buffer_Empty and FIFO_Write) or
                      (data_Exists_I and not FIFO_Read);
 
  Data_Exists_DFF : FDR
    port map (
      Q  => data_Exists_I,            -- [out std_logic]
      C  => Clk,                      -- [in  std_logic]
      D  => next_Data_Exists,         -- [in  std_logic]
      R  => Reset);                   -- [in std_logic]
 
  Data_Exists <= data_Exists_I;
  
  valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
 
  addr_cy(0) <= valid_Write;
 
  Addr_Counters : for I in 0 to 3 generate
 
    hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
 
    MUXCY_L_I : MUXCY_L
      port map (
        DI => addr_i(I),                  -- [in  std_logic]
        CI => addr_cy(I),               -- [in  std_logic]
        S  => hsum_A(I),                -- [in  std_logic]
        LO => addr_cy(I+1));            -- [out std_logic]
 
    XORCY_I : XORCY
      port map (
        LI => hsum_A(I),                -- [in  std_logic]
        CI => addr_cy(I),               -- [in  std_logic]
        O  => sum_A(I));                -- [out std_logic]
 
    FDRE_I : FDRE
      port map (
        Q  => addr_i(I),                  -- [out std_logic]
        C  => Clk,                      -- [in  std_logic]
        CE => data_Exists_I,            -- [in  std_logic]
        D  => sum_A(I),                 -- [in  std_logic]
        R  => Reset);                   -- [in std_logic]
 
  end generate Addr_Counters;
 
  FIFO_RAM : for I in 0 to C_DATA_BITS-1 generate
    SRL16E_I : SRL16E
      -- pragma translate_off
      generic map (
        INIT => x"0000")
      -- pragma translate_on
      port map (
        CE  => valid_Write,             -- [in  std_logic]
        D   => Data_In(I),              -- [in  std_logic]
        Clk => Clk,                     -- [in  std_logic]
        A0  => addr_i(0),                 -- [in  std_logic]
        A1  => addr_i(1),                 -- [in  std_logic]
        A2  => addr_i(2),                 -- [in  std_logic]
        A3  => addr_i(3),                 -- [in  std_logic]
        Q   => Data_Out(I));            -- [out std_logic]
  end generate FIFO_RAM;
  
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
  INT_ADDR_PROCESS:process (addr_i)
  begin   -- process
    Addr <= addr_i;
  end process;
  
 
end architecture IMP;
 
 
-------------------------------------------------------------------------------
-- axi_bram_ctrl_funcs.vhd
-------------------------------------------------------------------------------
--
--  
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES. 
--
--
------------------------------------------------------------------------------
-- Filename:        axi_bram_ctrl_funcs.vhd
--
-- Description:     Support functions for axi_bram_ctrl library modules.
--
-- VHDL-Standard:   VHDL'93
-------------------------------------------------------------------------------
--
--
-- History:
--
-- ^^^^^^
-- JLJ      2/1/2011         v1.03a
-- ~~~~~~
--  Migrate to v1.03a.
--  Plus minor code cleanup.
-- ^^^^^^
-- JLJ      2/16/2011      v1.03a
-- ~~~~~~
--  Update ECC size on 128-bit data width configuration.
-- ^^^^^^
-- JLJ      2/23/2011      v1.03a
-- ~~~~~~
--  Add MIG functions for Hsiao ECC.
-- ^^^^^^
-- JLJ      2/24/2011      v1.03a
-- ~~~~~~
--  Add Find_ECC_Size function.
-- ^^^^^^
-- JLJ      3/15/2011      v1.03a
-- ~~~~~~
--  Add REDUCTION_OR function.
-- ^^^^^^
-- JLJ      3/17/2011      v1.03a
-- ~~~~~~
--  Recode Create_Size_Max with a case statement.
-- ^^^^^^
-- JLJ      3/31/2011      v1.03a
-- ~~~~~~
--  Add coverage tags.
-- ^^^^^^
-- JLJ      5/6/2011      v1.03a
-- ~~~~~~
--  Remove usage of C_FAMILY.  
--  Remove Family_To_LUT_Size function.
--  Remove String_To_Family function.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x"
--      reset signals:                          "rst", "rst_n"
--      generics:                               "C_*"
--      user defined types:                     "*_TYPE"
--      state machine next state:               "*_ns"
--      state machine current state:            "*_cs"
--      combinatorial signals:                  "*_com"
--      pipelined or register delay signals:    "*_d#"
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce"
--      internal version of output port         "*_i"
--      device pins:                            "*_pin"
--      ports:                                  - Names begin with Uppercase
--      processes:                              "*_PROCESS"
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
 
package axi_bram_ctrl_funcs is
 
  type TARGET_FAMILY_TYPE is (
                              -- pragma xilinx_rtl_off
                              SPARTAN3,
                              VIRTEX4,
                              VIRTEX5,
                              SPARTAN3E,
                              SPARTAN3A,
                              SPARTAN3AN,
                              SPARTAN3Adsp,
                              SPARTAN6,
                              VIRTEX6,
                              VIRTEX7,
                              KINTEX7,
                              -- pragma xilinx_rtl_on
                              RTL
                             );
 
  -- function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE;
 
  -- Get the maximum number of inputs to a LUT.
  -- function Family_To_LUT_Size(Family : TARGET_FAMILY_TYPE) return integer;
 
  function Equal_String( str1, str2 : STRING ) RETURN BOOLEAN;
  function log2(x : natural) return integer;
  function Int_ECC_Size (i: integer) return integer;
  function Find_ECC_Size (i: integer; j: integer) return integer;
  function Find_ECC_Full_Bit_Size (i: integer; j: integer) return integer;
  function Create_Size_Max (i: integer) return std_logic_vector;
  function REDUCTION_OR (A: in std_logic_vector) return std_logic;
  function REDUCTION_XOR (A: in std_logic_vector) return std_logic;
  function REDUCTION_NOR (A: in std_logic_vector) return std_logic;
  function BOOLEAN_TO_STD_LOGIC (A: in BOOLEAN) return std_logic;
    
 
end package axi_bram_ctrl_funcs;
 
 
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
 
 
package body axi_bram_ctrl_funcs is
 
 
-------------------------------------------------------------------------------
-- Function:    Int_ECC_Size
-- Purpose:     Determine internal size of ECC when enabled.
-------------------------------------------------------------------------------
 
function Int_ECC_Size (i: integer) return integer is
begin  
 
--coverage off
 
    if (i = 32) then
        return 7;   -- 7-bits ECC for 32-bit data
                    -- ECC port size fixed @ 8-bits
    elsif (i = 64) then
        return 8;
    elsif (i = 128) then
        return 9;   -- Hsiao is 9-bits for 128-bit data.
    else
        return 0;
    end if;
 
--coverage on
    
end Int_ECC_Size;
 
-------------------------------------------------------------------------------
-- Function:    Find_ECC_Size
-- Purpose:     Determine external size of ECC signals when enabled.
-------------------------------------------------------------------------------
 
function Find_ECC_Size (i: integer; j: integer) return integer is
begin  
 
--coverage off
 
    if (i = 1) then
        if (j = 32) then
            return 8;   -- Keep at 8 for port size matchings
                        -- Only 7-bits ECC per 32-bit data
        elsif (j = 64) then
            return 8;
        elsif (j = 128) then
            return 9;
        else
            return 0;
        end if;
    else
        return 0;
        -- ECC data width = 0 when C_ECC = 0 (disabled)
    end if;
 
--coverage on
    
end Find_ECC_Size;
 
-------------------------------------------------------------------------------
-- Function:    Find_ECC_Full_Bit_Size
-- Purpose:     Determine external size of ECC signals when enabled in bytes.
-------------------------------------------------------------------------------
 
function Find_ECC_Full_Bit_Size (i: integer; j: integer) return integer is
begin  
 
--coverage off
 
    if (i = 1) then
        if (j = 32) then
            return 8;
        elsif (j = 64) then
            return 8;
        elsif (j = 128) then
            return 16;
        else
            return 0;
        end if;
    else
        return 0;
        -- ECC data width = 0 when C_ECC = 0 (disabled)
    end if;
 
--coverage on
    
end Find_ECC_Full_Bit_Size;
 
 
-------------------------------------------------------------------------------
-- Function:    Create_Size_Max
-- Purpose:     Create maximum value for AxSIZE based on AXI data bus width.
-------------------------------------------------------------------------------
 
function Create_Size_Max (i: integer)
    return std_logic_vector is
 
variable size_vector : std_logic_vector (2 downto 0);
begin
 
    case (i) is
        when 32 =>      size_vector := "010";           -- 2h (4 bytes)
        when 64 =>      size_vector := "011";           -- 3h (8 bytes)    
        when 128 =>     size_vector := "100";           -- 4h (16 bytes)
        when 256 =>     size_vector := "101";           -- 5h (32 bytes)
        when 512 =>     size_vector := "110";           -- 5h (32 bytes)
        when 1024 =>    size_vector := "111";           -- 5h (32 bytes)
--coverage off
        when others =>  size_vector := "000";           -- 0h    
--coverage on
 
    end case;
 
    return (size_vector);
 
end function Create_Size_Max;
 
 
 
 
 
-------------------------------------------------------------------------------
-- Function:    REDUCTION_OR
-- Purpose:     New in v1.03a
-------------------------------------------------------------------------------
 
function REDUCTION_OR (A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
    for i in A'range loop
       tmp := tmp or A(i);
    end loop;
    return tmp;
end function REDUCTION_OR;
 
 
 
 
-------------------------------------------------------------------------------
-- Function:    REDUCTION_XOR
-- Purpose:     Derived from MIG v3.7 ecc_gen module for use by Hsiao ECC.
--              New in v1.03a
-------------------------------------------------------------------------------
 
function REDUCTION_XOR (A: in std_logic_vector) return std_logic is
  variable tmp : std_logic := '0';
begin
  for i in A'range loop
       tmp := tmp xor A(i);
  end loop;
  return tmp;
end function REDUCTION_XOR;
 
 
 
 
-------------------------------------------------------------------------------
-- Function:    REDUCTION_NOR
-- Purpose:     Derived from MIG v3.7 ecc_dec_fix module for use by Hsiao ECC.
--              New in v1.03a
-------------------------------------------------------------------------------
 
function REDUCTION_NOR (A: in std_logic_vector) return std_logic is
  variable tmp : std_logic := '0';
begin
  for i in A'range loop
       tmp := tmp or A(i);
  end loop;
  return not tmp;
end function REDUCTION_NOR;
 
 
 
 
-------------------------------------------------------------------------------
-- Function:    BOOLEAN_TO_STD_LOGIC
-- Purpose:     Derived from MIG v3.7 ecc_dec_fix module for use by Hsiao ECC.
--              New in v1.03a
-------------------------------------------------------------------------------
 
function BOOLEAN_TO_STD_LOGIC (A : in BOOLEAN) return std_logic is
begin
   if A = true then
       return '1';
   else
       return '0';
   end if;
end function BOOLEAN_TO_STD_LOGIC;
 
 
-------------------------------------------------------------------------------
 
function LowerCase_Char(char : character) return character is
begin
 
--coverage off
 
    -- If char is not an upper case letter then return char
    if char < 'A' or char > 'Z' then
      return char;
    end if;
    -- Otherwise map char to its corresponding lower case character and
    -- return that
    case char is
      when 'A'    => return 'a'; when 'B' => return 'b'; when 'C' => return 'c'; when 'D' => return 'd';
      when 'E'    => return 'e'; when 'F' => return 'f'; when 'G' => return 'g'; when 'H' => return 'h';
      when 'I'    => return 'i'; when 'J' => return 'j'; when 'K' => return 'k'; when 'L' => return 'l';
      when 'M'    => return 'm'; when 'N' => return 'n'; when 'O' => return 'o'; when 'P' => return 'p';
      when 'Q'    => return 'q'; when 'R' => return 'r'; when 'S' => return 's'; when 'T' => return 't';
      when 'U'    => return 'u'; when 'V' => return 'v'; when 'W' => return 'w'; when 'X' => return 'x';
      when 'Y'    => return 'y'; when 'Z' => return 'z';
      when others => return char;
    end case;
 
--coverage on
 
end LowerCase_Char;
 
 
-------------------------------------------------------------------------------
 
 
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function Equal_String ( str1, str2 : STRING ) RETURN BOOLEAN IS
  CONSTANT len1 : INTEGER := str1'length;
  CONSTANT len2 : INTEGER := str2'length;
  VARIABLE equal : BOOLEAN := TRUE;
BEGIN
 
--coverage off
 
    IF NOT (len1=len2) THEN
      equal := FALSE;
    ELSE
      FOR i IN str1'range LOOP
        IF NOT (LowerCase_Char(str1(i)) = LowerCase_Char(str2(i))) THEN
          equal := FALSE;
        END IF;
      END LOOP;
    END IF;
 
--coverage on
 
    RETURN equal;
    
END Equal_String;
 
 
-------------------------------------------------------------------------------
 
 
-- Remove usage of C_FAMILY.
-- Remove usage of String_To_Family function.
--
--    
--    function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE is
--    begin  -- function String_To_Family
--    
--    --coverage off
--    
--        if ((Select_RTL) or Equal_String(S, "rtl")) then
--          return RTL;
--        elsif Equal_String(S, "spartan3") or Equal_String(S, "aspartan3") then
--          return SPARTAN3;
--        elsif Equal_String(S, "spartan3E") or Equal_String(S, "aspartan3E") then
--          return SPARTAN3E;
--        elsif Equal_String(S, "spartan3A") or Equal_String(S, "aspartan3A") then
--          return SPARTAN3A;
--        elsif Equal_String(S, "spartan3AN") then
--          return SPARTAN3AN;
--        elsif Equal_String(S, "spartan3Adsp") or Equal_String(S, "aspartan3Adsp") then
--          return SPARTAN3Adsp;
--        elsif Equal_String(S, "spartan6")  or Equal_String(S, "spartan6l") or
--              Equal_String(S, "qspartan6") or Equal_String(S, "aspartan6") or Equal_String(S, "qspartan6l") then
--          return SPARTAN6;
--        elsif Equal_String(S, "virtex4") or Equal_String(S, "qvirtex4")
--           or Equal_String(S, "qrvirtex4") then
--          return VIRTEX4;
--        elsif Equal_String(S, "virtex5") or Equal_String(S, "qrvirtex5") then
--          return VIRTEX5;
--        elsif Equal_String(S, "virtex6") or Equal_String(S, "virtex6l") or Equal_String(S, "qvirtex6") then
--          return VIRTEX6;
--        elsif Equal_String(S, "virtex7") then
--          return VIRTEX7;
--        elsif Equal_String(S, "kintex7") then
--          return KINTEX7;
--    
--    --coverage on
--    
--        else
--          -- assert (false) report "No known target family" severity failure;
--          return RTL;
--        end if;
--        
--    end function String_To_Family;
 
 
-------------------------------------------------------------------------------
 
-- Remove usage of C_FAMILY.
-- Remove usage of Family_To_LUT_Size function.
--
--    function Family_To_LUT_Size (Family : TARGET_FAMILY_TYPE) return integer is
--    begin
--    
--    --coverage off
--    
--        if (Family = SPARTAN3) or (Family = SPARTAN3E) or (Family = SPARTAN3A) or
--           (Family = SPARTAN3AN) or (Family = SPARTAN3Adsp) or (Family = VIRTEX4) then
--          return 4;
--        end if;
--    
--        return 6;
--    
--    --coverage on
--    
--    end function Family_To_LUT_Size;
 
 
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
--   x = 0  returns 0
--   x = 1  returns 0
--   x = 2  returns 1
--   x = 4  returns 2, etc.
-------------------------------------------------------------------------------
 
function log2(x : natural) return integer is
  variable i  : integer := 0; 
  variable val: integer := 1;
begin 
 
--coverage off
 
    if x = 0 then return 0;
    else
      for j in 0 to 29 loop -- for loop for XST 
        if val >= x then null; 
        else
          i := i+1;
          val := val*2;
        end if;
      end loop;
    -- Fix per CR520627  XST was ignoring this anyway and printing a  
    -- Warning in SRP file. This will get rid of the warning and not
    -- impact simulation.  
    -- synthesis translate_off
      assert val >= x
        report "Function log2 received argument larger" &
               " than its capability of 2^30. "
        severity failure;
    -- synthesis translate_on
      return i;
    end if;  
 
--coverage on
 
end function log2; 
 
 
-------------------------------------------------------------------------------
 
 
  
 
end package body axi_bram_ctrl_funcs;
 
 
-------------------------------------------------------------------------------
-- coregen_comp_defs - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
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-- ** The Xilinx Support Hotline does not have access to source           **
-- ** code and therefore cannot answer specific questions related         **
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-- ** code IP shall only address issues and questions related             **
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-- ** indirectly, the original core source).                              **
-- **                                                                     **
-- ** Copyright (c) 2008-2013 Xilinx, Inc. All rights reserved.           **
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-- **                                                                     **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        coregen_comp_defs.vhd
-- Version:         initial
-- Description:     
--   Component declarations for all black box netlists generated by
--   running COREGEN and AXI BRAM CTRL when XST elaborated the client core
--
-- VHDL-Standard:   VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--                      -- coregen_comp_defs.vhd
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
PACKAGE coregen_comp_defs IS
 
-------------------------------------------------------------------------------------
-- Start Block Memory Generator Component for blk_mem_gen_v8_3_6
-- Component declaration for blk_mem_gen_v8_3_6 pulled from the  blk_mem_gen_v8_3_6.v
-- Verilog file used to match paramter order for NCSIM compatibility
-------------------------------------------------------------------------------------
component blk_mem_gen_v8_3_6
  generic (
  ----------------------------------------------------------------------------
  -- Generic Declarations
  ----------------------------------------------------------------------------
  --Device Family & Elaboration Directory Parameters:
    C_FAMILY                    : STRING  := "virtex4";
    C_XDEVICEFAMILY             : STRING  := "virtex4";
--    C_ELABORATION_DIR           : STRING  := "";
  
    C_INTERFACE_TYPE            : INTEGER := 0;
    C_AXI_TYPE                  : INTEGER := 1;
    C_AXI_SLAVE_TYPE            : INTEGER := 0;
    C_HAS_AXI_ID                : INTEGER := 0;
 
    C_AXI_ID_WIDTH                : INTEGER := 4;
  --General Memory Parameters:  
    C_MEM_TYPE                  : INTEGER := 2;
    C_BYTE_SIZE                 : INTEGER := 9;
    C_ALGORITHM                 : INTEGER := 0;
    C_PRIM_TYPE                 : INTEGER := 3;
  
  --Memory Initialization Parameters:
    C_LOAD_INIT_FILE            : INTEGER := 0;
    C_INIT_FILE_NAME            : STRING  := "";
    C_USE_DEFAULT_DATA          : INTEGER := 0;
    C_DEFAULT_DATA              : STRING  := "111111111";
    C_RST_TYPE                  : STRING  := "SYNC";
  
  --Port A Parameters:
    --Reset Parameters:
    C_HAS_RSTA                  : INTEGER := 0;
    C_RST_PRIORITY_A            : STRING  := "CE";
    C_RSTRAM_A                  : INTEGER := 0;
    C_INITA_VAL                 : STRING  := "0";
  
    --Enable Parameters:
    C_HAS_ENA                   : INTEGER := 1;
    C_HAS_REGCEA                : INTEGER := 0;
  
    --Byte Write Enable Parameters:
    C_USE_BYTE_WEA              : INTEGER := 0;
    C_WEA_WIDTH                 : INTEGER := 1;
  
    --Write Mode:
    C_WRITE_MODE_A              : STRING  := "WRITE_FIRST";
  
    --Data-Addr Width Parameters:
    C_WRITE_WIDTH_A             : INTEGER := 4;
    C_READ_WIDTH_A              : INTEGER := 4;
    C_WRITE_DEPTH_A             : INTEGER := 4096;
    C_READ_DEPTH_A              : INTEGER := 4096;
    C_ADDRA_WIDTH               : INTEGER := 12;
  
  --Port B Parameters:
    --Reset Parameters:
    C_HAS_RSTB                  : INTEGER := 0;
    C_RST_PRIORITY_B            : STRING  := "CE";
    C_RSTRAM_B                  : INTEGER := 0;
    C_INITB_VAL                 : STRING  := "0";
  
    --Enable Parameters:
    C_HAS_ENB                   : INTEGER := 1;
    C_HAS_REGCEB                : INTEGER := 0;
  
    --Byte Write Enable Parameters:
    C_USE_BYTE_WEB              : INTEGER := 0;
    C_WEB_WIDTH                 : INTEGER := 1;
  
    --Write Mode:
    C_WRITE_MODE_B              : STRING  := "WRITE_FIRST";
  
    --Data-Addr Width Parameters:
    C_WRITE_WIDTH_B             : INTEGER := 4;
    C_READ_WIDTH_B              : INTEGER := 4;
    C_WRITE_DEPTH_B             : INTEGER := 4096;
    C_READ_DEPTH_B              : INTEGER := 4096;
    C_ADDRB_WIDTH               : INTEGER := 12;
  
  --Output Registers/ Pipelining Parameters:
    C_HAS_MEM_OUTPUT_REGS_A     : INTEGER := 0;
    C_HAS_MEM_OUTPUT_REGS_B     : INTEGER := 0;
    C_HAS_MUX_OUTPUT_REGS_A     : INTEGER := 0;
    C_HAS_MUX_OUTPUT_REGS_B     : INTEGER := 0;
    C_MUX_PIPELINE_STAGES       : INTEGER := 0;
 
   --Input/Output Registers for SoftECC :
    C_HAS_SOFTECC_INPUT_REGS_A  : INTEGER := 0;
    C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
  
  --ECC Parameters
    C_USE_ECC                   : INTEGER := 0;
    C_USE_SOFTECC               : INTEGER := 0;
    C_HAS_INJECTERR             : INTEGER := 0;
    
  --Simulation Model Parameters:
    C_SIM_COLLISION_CHECK       : STRING  := "NONE";
    C_COMMON_CLK                : INTEGER := 0;
    C_DISABLE_WARN_BHV_COLL     : INTEGER := 0;
    C_DISABLE_WARN_BHV_RANGE    : INTEGER := 0
  );
  PORT (
  ----------------------------------------------------------------------------
  -- Input and Output Declarations
  ----------------------------------------------------------------------------
  -- Native BMG Input and Output Port Declarations
  --Port A:
    CLKA                             : IN  STD_LOGIC := '0';
    RSTA                             : IN  STD_LOGIC := '0';
    ENA                              : IN  STD_LOGIC := '0';
    REGCEA                           : IN  STD_LOGIC := '0';
    WEA                              : IN  STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
    ADDRA                            : IN  STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
    DINA                             : IN  STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
    DOUTA                            : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
  
  --Port B:
    CLKB                             : IN  STD_LOGIC := '0';
    RSTB                             : IN  STD_LOGIC := '0';
    ENB                              : IN  STD_LOGIC := '0';
    REGCEB                           : IN  STD_LOGIC := '0';
    WEB                              : IN  STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
    ADDRB                            : IN  STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
    DINB                             : IN  STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
    DOUTB                            : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
  
  --ECC:
    INJECTSBITERR                    : IN  STD_LOGIC := '0';
    INJECTDBITERR                    : IN  STD_LOGIC := '0';
    SBITERR                          : OUT STD_LOGIC;
    DBITERR                          : OUT STD_LOGIC;
    RDADDRECC                        : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
  -- AXI BMG Input and Output Port Declarations
 
    -- AXI Global Signals
    S_AClk                         : IN  STD_LOGIC := '0';
    S_ARESETN                      : IN  STD_LOGIC := '0'; 
 
    -- AXI Full/Lite Slave Write (write side)
    S_AXI_AWID                     : IN  STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
    S_AXI_AWADDR                   : IN  STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
    S_AXI_AWLEN                    : IN  STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
    S_AXI_AWSIZE                   : IN  STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
    S_AXI_AWBURST                  : IN  STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
    S_AXI_AWVALID                  : IN  STD_LOGIC := '0';
    S_AXI_AWREADY                  : OUT STD_LOGIC;
    S_AXI_WDATA                    : IN  STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
    S_AXI_WSTRB                    : IN  STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
    S_AXI_WLAST                    : IN  STD_LOGIC := '0';
    S_AXI_WVALID                   : IN  STD_LOGIC := '0';
    S_AXI_WREADY                   : OUT STD_LOGIC;
    S_AXI_BID                      : OUT  STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
    S_AXI_BRESP                    : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
    S_AXI_BVALID                   : OUT STD_LOGIC;
    S_AXI_BREADY                   : IN  STD_LOGIC := '0';
 
    -- AXI Full/Lite Slave Read (Write side)
    S_AXI_ARID                     : IN  STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
    S_AXI_ARADDR                   : IN  STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
    S_AXI_ARLEN                    : IN  STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
    S_AXI_ARSIZE                   : IN  STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
    S_AXI_ARBURST                  : IN  STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
    S_AXI_ARVALID                  : IN  STD_LOGIC := '0';
    S_AXI_ARREADY                  : OUT STD_LOGIC;
    S_AXI_RID                      : OUT  STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
    S_AXI_RDATA                    : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0); 
    S_AXI_RRESP                    : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
    S_AXI_RLAST                    : OUT STD_LOGIC;
    S_AXI_RVALID                   : OUT STD_LOGIC;
    S_AXI_RREADY                   : IN  STD_LOGIC := '0';
 
    -- AXI Full/Lite Sideband Signals
    S_AXI_INJECTSBITERR              : IN  STD_LOGIC := '0';
    S_AXI_INJECTDBITERR              : IN  STD_LOGIC := '0';
    S_AXI_SBITERR                    : OUT STD_LOGIC;
    S_AXI_DBITERR                    : OUT STD_LOGIC;
    S_AXI_RDADDRECC                  : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
 
  );
 
  END COMPONENT; --blk_mem_gen_v8_3_6
 
END coregen_comp_defs;
 
 
-------------------------------------------------------------------------------
-- axi_lite_if.vhd
-------------------------------------------------------------------------------
--
--  
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES. 
--
--
-------------------------------------------------------------------------------
-- Filename:        axi_lite_if.vhd
--
-- Description:     Derived AXI-Lite interface module.
--                  
-- VHDL-Standard:   VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
--              axi_bram_ctrl.vhd (v1_03_a)
--                      |
--                      |-- full_axi.vhd
--                      |   -- sng_port_arb.vhd
--                      |   -- lite_ecc_reg.vhd
--                      |       -- axi_lite_if.vhd
--                      |   -- wr_chnl.vhd
--                      |       -- wrap_brst.vhd
--                      |       -- ua_narrow.vhd
--                      |       -- checkbit_handler.vhd
--                      |           -- xor18.vhd
--                      |           -- parity.vhd
--                      |       -- checkbit_handler_64.vhd
--                      |           -- (same helper components as checkbit_handler)
--                      |       -- parity.vhd
--                      |       -- correct_one_bit.vhd
--                      |       -- correct_one_bit_64.vhd
--                      |
--                      |   -- rd_chnl.vhd
--                      |       -- wrap_brst.vhd
--                      |       -- ua_narrow.vhd
--                      |       -- checkbit_handler.vhd
--                      |           -- xor18.vhd
--                      |           -- parity.vhd
--                      |       -- checkbit_handler_64.vhd
--                      |           -- (same helper components as checkbit_handler)
--                      |       -- parity.vhd
--                      |       -- correct_one_bit.vhd
--                      |       -- correct_one_bit_64.vhd
--                      |
--                      |-- axi_lite.vhd
--                      |   -- lite_ecc_reg.vhd
--                      |       -- axi_lite_if.vhd
--                      |   -- checkbit_handler.vhd
--                      |       -- xor18.vhd
--                      |       -- parity.vhd
--                      |   -- checkbit_handler_64.vhd
--                      |       -- (same helper components as checkbit_handler)
--                      |   -- correct_one_bit.vhd
--                      |   -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ      2/1/2011         v1.03a
-- ~~~~~~
--  Migrate to v1.03a.
--  Plus minor code cleanup.
-- ^^^^^^
--                            
--
-- 
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
entity axi_lite_if is
  generic (
    -- AXI4-Lite slave generics
    -- C_S_AXI_BASEADDR        : std_logic_vector       := X"FFFF_FFFF";
    -- C_S_AXI_HIGHADDR        : std_logic_vector       := X"0000_0000";
    C_S_AXI_ADDR_WIDTH      : integer                := 32;
    C_S_AXI_DATA_WIDTH      : integer                := 32;
    C_REGADDR_WIDTH         : integer                := 4;    -- Address bits including register offset.
    C_DWIDTH                : integer                := 32);  -- Width of data bus.
  port (
    LMB_Clk : in std_logic;
    LMB_Rst : in std_logic;
 
    -- AXI4-Lite SLAVE SINGLE INTERFACE
    S_AXI_AWADDR  : in  std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
    S_AXI_AWVALID : in  std_logic;
    S_AXI_AWREADY : out std_logic;
    S_AXI_WDATA   : in  std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
    S_AXI_WSTRB   : in  std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
    S_AXI_WVALID  : in  std_logic;
    S_AXI_WREADY  : out std_logic;
    S_AXI_BRESP   : out std_logic_vector(1 downto 0);
    S_AXI_BVALID  : out std_logic;
    S_AXI_BREADY  : in  std_logic;
    S_AXI_ARADDR  : in  std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
    S_AXI_ARVALID : in  std_logic;
    S_AXI_ARREADY : out std_logic;
    S_AXI_RDATA   : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
    S_AXI_RRESP   : out std_logic_vector(1 downto 0);
    S_AXI_RVALID  : out std_logic;
    S_AXI_RREADY  : in  std_logic;
    
    -- lmb_bram_if_cntlr signals
    RegWr         : out std_logic;
    RegWrData     : out std_logic_vector(0 to C_DWIDTH - 1);
    RegAddr       : out std_logic_vector(0 to C_REGADDR_WIDTH-1);  
    RegRdData     : in  std_logic_vector(0 to C_DWIDTH - 1));
end entity axi_lite_if;
 
library unisim;
use unisim.vcomponents.all;
 
architecture IMP of axi_lite_if is
 
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
 
  -----------------------------------------------------------------------------
  -- Signal declaration
  -----------------------------------------------------------------------------
  signal new_write_access       : std_logic;
  signal new_read_access        : std_logic;
  signal ongoing_write          : std_logic;
  signal ongoing_read           : std_logic;
 
  signal S_AXI_RVALID_i         : std_logic;
 
  signal RegRdData_i            : std_logic_vector(C_DWIDTH - 1 downto 0);
 
begin  -- architecture IMP
 
  -----------------------------------------------------------------------------
  -- Handling the AXI4-Lite bus interface (AR/AW/W)
  -----------------------------------------------------------------------------
  
  -- Detect new transaction.
  -- Only allow one access at a time
  new_write_access  <= not (ongoing_read or ongoing_write) and S_AXI_AWVALID and S_AXI_WVALID;
  new_read_access   <= not (ongoing_read or ongoing_write) and S_AXI_ARVALID and not new_write_access;
 
  -- Acknowledge new transaction.
  S_AXI_AWREADY <= new_write_access;
  S_AXI_WREADY  <= new_write_access;
  S_AXI_ARREADY <= new_read_access;
 
  -- Store register address and write data 
  Reg: process (LMB_Clk) is
  begin
    if LMB_Clk'event and LMB_Clk = '1' then
      if LMB_Rst = '1' then
        RegAddr   <= (others => '0');
        RegWrData <= (others => '0');
      elsif new_write_access = '1' then
        RegAddr   <= S_AXI_AWADDR(C_REGADDR_WIDTH-1+2 downto 2);
        RegWrData <= S_AXI_WDATA(C_DWIDTH-1 downto 0);
      elsif new_read_access = '1' then
        RegAddr   <= S_AXI_ARADDR(C_REGADDR_WIDTH-1+2 downto 2);
      end if;
    end if;
  end process Reg;
  
  -- Handle write access.
  WriteAccess: process (LMB_Clk) is
  begin
    if LMB_Clk'event and LMB_Clk = '1' then
      if LMB_Rst = '1' then
        ongoing_write <= '0';
      elsif new_write_access = '1' then
        ongoing_write <= '1';
      elsif ongoing_write = '1' and S_AXI_BREADY = '1' then
        ongoing_write <= '0';
      end if;
      RegWr <= new_write_access;
    end if;
  end process WriteAccess;
 
  S_AXI_BVALID <= ongoing_write;
  S_AXI_BRESP  <= (others => '0');
 
  -- Handle read access
  ReadAccess: process (LMB_Clk) is
  begin
    if LMB_Clk'event and LMB_Clk = '1' then
      if LMB_Rst = '1' then
        ongoing_read   <= '0';
        S_AXI_RVALID_i <= '0';
      elsif new_read_access = '1' then
        ongoing_read   <= '1';
        S_AXI_RVALID_i <= '0';
      elsif ongoing_read = '1' then
        if S_AXI_RREADY = '1' and S_AXI_RVALID_i = '1' then
          ongoing_read   <= '0';
          S_AXI_RVALID_i <= '0';
        else
          S_AXI_RVALID_i <= '1'; -- Asserted one cycle after ongoing_read to match S_AXI_RDDATA
        end if;
      end if;
    end if;
  end process ReadAccess;
 
  S_AXI_RVALID <= S_AXI_RVALID_i;
  S_AXI_RRESP  <= (others => '0');
  
  Not_All_Bits_Are_Used: if (C_DWIDTH < C_S_AXI_DATA_WIDTH) generate
  begin
    S_AXI_RDATA(C_S_AXI_DATA_WIDTH-1 downto C_S_AXI_DATA_WIDTH - C_DWIDTH)  <= (others=>'0');
  end generate Not_All_Bits_Are_Used;
 
  RegRdData_i <= RegRdData;             -- Swap to - downto
  
  S_AXI_RDATA_DFF : for I in C_DWIDTH - 1 downto 0 generate
  begin
    S_AXI_RDATA_FDRE : FDRE
      port map (
        Q  => S_AXI_RDATA(I),
        C  => LMB_Clk,
        CE => ongoing_read,
        D  => RegRdData_i(I),
        R  => LMB_Rst);
  end generate S_AXI_RDATA_DFF;
  
end architecture IMP;
 
 
-------------------------------------------------------------------------------
-- checkbit_handler_64.vhd
-------------------------------------------------------------------------------
--
--  
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES. 
--
--
-------------------------------------------------------------------------------
-- Filename:        checkbit_handler_64.vhd
--
-- Description:     Generates the ECC checkbits for the input vector of 
--                  64-bit data widths.
--                  
-- VHDL-Standard:   VHDL'93/02
--
-------------------------------------------------------------------------------
-- Structure:   
--              axi_bram_ctrl.vhd (v1_03_a)
--                      |
--                      |-- full_axi.vhd
--                      |   -- sng_port_arb.vhd
--                      |   -- lite_ecc_reg.vhd
--                      |       -- axi_lite_if.vhd
--                      |   -- wr_chnl.vhd
--                      |       -- wrap_brst.vhd
--                      |       -- ua_narrow.vhd
--                      |       -- checkbit_handler.vhd
--                      |           -- xor18.vhd
--                      |           -- parity.vhd
--                      |       -- checkbit_handler_64.vhd
--                      |           -- (same helper components as checkbit_handler)
--                      |       -- parity.vhd
--                      |       -- correct_one_bit.vhd
--                      |       -- correct_one_bit_64.vhd
--                      |
--                      |   -- rd_chnl.vhd
--                      |       -- wrap_brst.vhd
--                      |       -- ua_narrow.vhd
--                      |       -- checkbit_handler.vhd
--                      |           -- xor18.vhd
--                      |           -- parity.vhd
--                      |       -- checkbit_handler_64.vhd
--                      |           -- (same helper components as checkbit_handler)
--                      |       -- parity.vhd
--                      |       -- correct_one_bit.vhd
--                      |       -- correct_one_bit_64.vhd
--                      |
--                      |-- axi_lite.vhd
--                      |   -- lite_ecc_reg.vhd
--                      |       -- axi_lite_if.vhd
--                      |   -- checkbit_handler.vhd
--                      |       -- xor18.vhd
--                      |       -- parity.vhd
--                      |   -- checkbit_handler_64.vhd
--                      |       -- (same helper components as checkbit_handler)
--                      |   -- correct_one_bit.vhd
--                      |   -- correct_one_bit_64.vhd
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ      2/2/2011         v1.03a
-- ~~~~~~
--  Migrate to v1.03a.
--  Plus minor code cleanup.
-- ^^^^^^
--
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
 
entity checkbit_handler_64 is
  generic (
    C_ENCODE   : boolean := true;
    C_REG      : boolean := false;
    C_USE_LUT6 : boolean := true);
  port (
 
    Clk             : in    std_logic;
 
    DataIn          : in  std_logic_vector (63 downto 0);
    CheckIn         : in  std_logic_vector (7 downto 0);
    CheckOut        : out std_logic_vector (7 downto 0);
    Syndrome        : out std_logic_vector (7 downto 0);
    Syndrome_7      : out std_logic_vector (11 downto 0);
    Syndrome_Chk    : in  std_logic_vector (0 to 7);    
 
    Enable_ECC : in  std_logic;
    UE_Q       : in  std_logic;
    CE_Q       : in  std_logic;
    UE         : out std_logic;
    CE         : out std_logic
    );
    
end entity checkbit_handler_64;
 
library unisim;
use unisim.vcomponents.all;
 
-- library axi_bram_ctrl_v1_02_a;
-- use axi_bram_ctrl_v1_02_a.all;
 
architecture IMP of checkbit_handler_64 is
 
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
 
  component XOR18 is
    generic (
      C_USE_LUT6 : boolean);
    port (
      InA : in  std_logic_vector(0 to 17);
      res : out std_logic);
  end component XOR18;
  
  component Parity is
    generic (
      C_USE_LUT6 : boolean;
      C_SIZE     : integer);
    port (
      InA : in  std_logic_vector(0 to C_SIZE - 1);
      Res : out std_logic);
  end component Parity;
 
 --    component ParityEnable
 --      generic (
 --        C_USE_LUT6 : boolean;
 --        C_SIZE     : integer);
 --      port (
 --        InA    : in  std_logic_vector(0 to C_SIZE - 1);
 --        Enable : in  std_logic;
 --        Res    : out std_logic);
 --    end component ParityEnable;
  
  
  signal data_chk0          : std_logic_vector(0 to 34);
  signal data_chk1          : std_logic_vector(0 to 34);
  signal data_chk2          : std_logic_vector(0 to 34);
  signal data_chk3          : std_logic_vector(0 to 30);
  signal data_chk4          : std_logic_vector(0 to 30);
  signal data_chk5          : std_logic_vector(0 to 30);
  
  signal data_chk6          : std_logic_vector(0 to 6);
  signal data_chk6_xor      : std_logic;
  
  -- signal data_chk7_a        : std_logic_vector(0 to 17);
  -- signal data_chk7_b        : std_logic_vector(0 to 17);
  -- signal data_chk7_i        : std_logic;
  -- signal data_chk7_xor      : std_logic;
  -- signal data_chk7_i_xor    : std_logic;
  -- signal data_chk7_a_xor      : std_logic;
  -- signal data_chk7_b_xor    : std_logic;
 
  
begin  -- architecture IMP
 
 
    -- Add bits for 64-bit ECC
    
    -- 0 <= 0 1 3 4 6 8 10 11 13 17 19 21 23 25 26 28 30 
    --      32 34 36 38 40 42 44 46 48 50 52 54 56 57 59 61 63 
 
  data_chk0 <= DataIn(0) & DataIn(1) & DataIn(3) & DataIn(4) & DataIn(6) & DataIn(8) & DataIn(10) &
               DataIn(11) & DataIn(13) & DataIn(15) & DataIn(17) & DataIn(19) & DataIn(21) &
               DataIn(23) & DataIn(25) & DataIn(26) & DataIn(28) & DataIn(30) &
               
               DataIn(32) & DataIn(34) & DataIn(36) & DataIn(38) &