assign initail value to signal

[mrflibble]

Good discussion, food for thought.

Note that I am mostly concerned with fpga, as said here:

"So if your design is intended to always target an fpga (i.e no plans for ASICs or some such), then as far as I can tell there is no need to ALWAYS do an explicit reset for everything."

Regarding usage of the initial statement, see for example some recommendations regarding the spartan-6. Page 15 of this one: https://www.xilinx.com/support/documentation/user_guides/ug384.pdf

SRINIT0 and SRINIT1 can be set individually for each storage element in a slice. The choice
of synchronous (SYNC) or asynchronous (ASYNC) set/reset (SRTYPE) is common to all
eight storage elements and cannot be set individually for each storage element in a slice.

The initial state after configuration or global initial state is also defined by the same SRINIT
option. The initial state is set whenever the Global Set/Reset (GSR) signal is asserted. The
GSR signal is always asserted during configuration, and can be controlled after
configuration by using the STARTUP_SPARTAN6 primitive. To maximize design
flexibility and utilization, use the GSR and avoid local initialization signals.

The initial state of any storage element (SRINIT) is defined in the design either by the INIT
attribute or by the use of a set or reset. If both methods are used, they must both be 0 or
both be 1. INIT = 0 or a reset selects SRINIT0, and INIT = 1 or a set selects SRINIT1.

Anyways, lots of good points have been made. Busy reading.