electronical
Advanced Member level 4
hello, how can i assign initail value to signal without using process?
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Hi,I write this code but when I synt ,I face with this error:
package my_package is
type matrix1x8 is array ( 1 to 8) of integer range -127 to 127;
end package;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_logic_unsigned.all;
use work.my_package.all;
entity as is
port(clk,clr,reset:in bit;col_L:in matrix1x8
...);
end;
architecture behave of new_min_value is
signal a:integer range -127 to 127 :=1;
signal ii:integer range 1 to 8;
signal Mes_c_to_v:integer range -127 to 127:=1;
signal out_1:integer range -127 to 127:=1;
signal d:integer range -127 to 127:=1;
signal Lnew:integer range -127 to 127:=1;
begin
.
.
.
a<=col_L(ii);
d<=a-Mes_c_to_v;
...
process(clk,reset,clr )
variable i:integer range 0 to 8;
begin
if reset ='1' then
i:=0;
else
if (clk 'event and clk='1' )then
if clr='1' then
if i=8 then
i:=1;
else
i:=i+1;ii<=i;
end if;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------------------
;
end;
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------------------------------------signal a:integer range -127 to 127 :=1;
signal Mes_c_to_v:integer range -127 to 127:=1;d<=a-Mes_c_to_v;
Are you sure it's a bad idea? In the past I've read some conflicting opinions about it. Because I also used to use explicit reset circuitry in fpga's ... because the folk wisdom said so. But as usual with folk wisdom, these folks should update their wisdom more often!
While explicit reset code for everything in your HDL looks nice and clean, and makes you a better and happier person, there's a flip-side to it. All those nice reset lines (and of course there is going to be more than one
Resets uses circuitry and routed wires, whereas initial values use nothing. They're completely different.
There is a very good engineering reason and it has nothing to do with 'folk wisdom' or 'opinions'. It's also a very simple explanation best explained by considering the following:
The flip side also is that reset code can (and should be) designed to meet timing requirements. Specifically, 'reset' needs to go inactive at a known time relative to the clock. If you have multiple clocks, then you need seperate resets signals for each clock domain. A dual clock fifo? You hope that the designer knows what they were doing.While explicit reset code for everything in your HDL looks nice and clean, and makes you a better and happier person, there's a flip-side to it. All those nice reset lines (and of course there is going to be more than one
- There is rarely a need to reset everything. Certain key things do need to be reset somehow, examples being the state of a state machine. Many flip flops do not need to be reset, examples being pretty much the entire data path. While reset can still have a lot of loads, the number of flops dedicated to data path that do not need to be reset will far outnumber the state machine, control and status bits that do need to be reset.
Most FPGAs allow to trigger configuration by an external signal, many are exposing an optional input feeding the POR net.
Which difference do you imagine? If reset is asynchronously released, there's no difference in timing behaviour I think. Of course reset can be applied on demand, and it can be originated from a reset synchronizer, which changes a lot.
I hear a lack of knowledge about actual FPGA hardware behind this statement. I'm not talking about ASICs.
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