Applying gate voltage more than VDD of CMOS analog circuit

Status
Not open for further replies.
J

Junus2012

Advanced Member level 5
Joined
Jan 9, 2012
Messages
1,552
Helped
47
Reputation
98
Reaction score
53
Trophy points
1,328
Location
Italy
Activity points
15,235
Hello,

I am working with CMOS 0.35 µm, 3.3 V technology standard technology.

Consider simple digital inverter as an example, and I want to apply an external input voltage of 5 V while the inverter is powered by 3.3 V. Will that cause a damage?, what is the relevant parameter that I can read on this voltage from the technology data sheet.

Thanks

Best Regards
 

You can't find it on the datasheet.

You care about long term BVox and any enhanced hot carrier effects
(you'd be outside any qualification testing, to say about HCE; a decent
test-to-fail series ought to deliver BVox / lifetime data on single devices
out to insta-fail voltage.

Now in my experience the BVox is going to be at least 2X, probably 3X
the supply voltage rating (depending on what the first fail mode is, for
the sum of all sensitivities).

But good luck getting "blessed" if nobody's plowed that road and got
waivers on file.

On the plus side, 0.35u is so mature that there's a chance this has happened.
 

    J

    Junus2012

    Points: 2
    Helpful Answer Positive Rating
An additional concern is, just where does this "5V" come from?
If a pin / pad then now you need ESD protection and that may
your much bigger challenge if all you have is 3.3V MOSFETs.

Look for "overvoltage tolerant CMOS input buffer" and see
schemes for blocking overvoltage and if you're lucky, hints
about over-rail pin protection.
 

    J

    Junus2012

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…