anyone used OpenCore i2c MasterCore successfully?

[mrflibble]

I'm transmitting data to FPGA by writing it on 'transmit register' using PIC programming in 8051, so i am confused what is input for sda_pad_i?

Your top level module should look something like:

top_level_module (
    // other stuff
    inout wire scl,
    inout wire sda,
    // still more stuff
    );

Then you connect the signals from the i2c module something like:

wire scl_pad_o;
wire sda_pad_o;

assign scl = (scl_pad_o == 1'b0) ? (1'b0) : (1'bz);
assign sda = (sda_pad_o == 1'b0) ? (1'b0) : (1'bz);

i2c_core_module_name   example_instance (
    .scl_pad_o(scl_pad_o),
    .sda_pad_o(sda_pad_o),
    .sda_pad_i(sda),
    // etc
    );

This will synthesize to open-collector outputs.

For simulation, you'll have to add a couple of pullups to the sda and scl lines. If you don't then the high signal levels will show as Z's in the simulation.

 

[saurabhbhavsar19]

my top level module is

---

Code VHDL - [expand]
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entity i2c_master_top is
    generic(
            ARST_LVL : std_logic := '0'                   
    );
    port   (
               // other stuff
               scl_pad_i     : in  std_logic;                    -- i2c clock line input
               scl_pad_o     : out std_logic;                    -- i2c clock line output
               scl_padoen_o  : out std_logic;                    -- i2c clock line output enable, active low
               
               sda_pad_i     : in  std_logic;                    -- i2c data line input
               sda_pad_o     : out std_logic;                    -- i2c data line output
               sda_padoen_o  : out std_logic                     -- i2c data line output enable, active low
               ); end entity i2c_master_top;

---

since it is inout.i m confused ,what should i connect to its input?

 

[mrflibble]

Your confusion confuses me. Didn't I just post what connects to what for the inouts?

 

[saurabhbhavsar19]

can you plz suggest code in vhdl.plz

 

[mrflibble]

I could. But I won't. I am not all that great with vhdl...

Why not google "vhdl open collector tristate"?

 

[saurabhbhavsar19]

plz plz give me vhdl code for implementing tri-state buffer for i2c lines(scl_pad_i,scl_pad_o,scl_pad_oe,etc)

 

[mrflibble]

Well, I just did 10 seconds of googling and found it. So, uhm, go do that. It will be a character building experience!

---------- Post added at 11:49 ---------- Previous post was at 11:45 ----------

Oh alright, I am feeling nice today even towards the complacent lazy people of the world.

So there you go! First 2 google hits for "vhdl tristate inout".

https://www.edaboard.com/threads/55243/
VHDL:Tri-State Buses

 

[Ekiga]

Just wanted to warn people to be careful with using I2C fpga core as the voltage of I2c can be 5V pullup and most FPGA's these days don't go that high.

 

[Santosh Elangadi]

hello, i am interested in i2c-wishbone interface project. can u plz tell me

how to

1. Block diagram of i2c master and Design code (verilog)?

2. Block Diagram of Wishbone slave and design code(verilog)?

3. hoe to interface and design code(verilog)?

and mail me if u have report of any part

my email id is santoshelangadi@gmail.com, Awaiting your reply

 

[ads-ee]

sda_pad_i would be used to read data back from the DAC, if it allows reading.

I also have used the master I2C core (pre-wishbone interface) in a design. We had absolutely no problems controlling an RF module that was attached to our board. In our case the FPGA was the bridge between the 16-bit uProcessor and the I2C. As it was a bridge I didn't need to create an FSM to control any flash device.

 

[mrflibble]

hello, i am interested in i2c-wishbone interface project. can u plz tell me

how to

1. Block diagram of i2c master and Design code (verilog)?

2. Block Diagram of Wishbone slave and design code(verilog)?

3. hoe to interface and design code(verilog)?

and mail me if u have report of any part

my email id is santoshelangadi@gmail.com, Awaiting your reply

Noooo problem. To whom do I address the invoice?