anyone used OpenCore i2c MasterCore successfully?

[naz56]

anyone used OpenCore i2c MasterCore successfully?

YOUR help would be highly appreciated.
thanx

 

[sudhirkv]

Ya i have used.

Any problem

 

[naz56]

good to hear...actually that core works fine in modelsim..everything is running good in simulation...but i need simple top level module that can write and read data from serial eeprom....if you have gone through this task...then kindly give some hint or send simple top level module which also works fine on fpga board when downloaded on it..



i will be very thankfull to you...

thanx

 

[sudhirkv]

what is the serial eprom u r using.

probably the datasheet itself will give you the way to access the memory location.

I used this i2c core to access a RTC ds1388.

what i can suggest you is the manufacturer of the eprom will give you a software model to access the eprom mostly in C. u can see that program on how to access the data from serial eprom.

I folloowed the same way to get he time from rtc.

Just try it.

 

[naz56]

thanx sudhirkv

i am using ATMEL's 2 wire serial eeprom(AT24C256W) which uses i2c bus to communicate with fpga chip.yup datasheet is helpful but i have some confusion regarding opencore's i2c because of wishbone interface implemented in verilog.

 

[sudhirkv]

I dont know what exactly is your problem in wishbone interface.

in that i2c core wishbone interface you have to connect the address lines to the address line in the i2c wishbone and data bus to the dataline. The address bits help you to access the internal control and status registers.


Is your design having any microprocessor or a MicroController.

Please ellaborate your problem so that i can help you in detail.

 

[naz56]

in my design master is FPGA and slave is serial eeprom.
actually i dont know how to write top level module and how to give different commands in sequence? i need i2c test type module that will generate different commands in right sequence.hv to implement FSM or another module for testing this core?

thanx

 

[naz56]

????????
was that code for 3 wire serial eeprom?

 

[sudhirkv]

Sorry for the delay,

if u r not using any microprocessor or microcontroler u have to write a state machine to send comands to the I2C controller.

see this link on how they are accessing the serial eeprom using C follow the command sequence and try.\

**broken link removed**

all the best

 

[naz56]

but but but i hv implemented fsm to give different commands using VERILOG...but its seems not to be working...i hv given different commands on each posedge of clock..i have also tried to eliminate wishbone signals...n tried to write testing module that can also b synthesizable...but all in a vain..


u hv tried?
can u plz upload or copy paste over here so tht i could hv idea? so tht main modify kr k use krsakun..

i will be very thank full .



Added after 5 minutes:

i need Sample VHDL/ VERILOG code utilizing i2c master core..

 

[sudhirkv]

I simply included that I2C core to my code, in my case the processor will send the commands to i2c wishbone interface. If u r not using any uC then u have to go for a statemachine.

ok

Please explain ur design briefly so that i can suggest you some ideas. if possible a block diagram.

We will do it

Added after 2 minutes:

How u r debugging u r design

 

[naz56]

i need Sample VHDL/ VERILOG code utilizing i2c master core..(to send and receive some data to/from some i2c compatible memory chip....

here is a code without using wishbone (referencepencore.org)
check if it is ok...

***************************

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module i2c_master_top(clk, rst, i2c_rst,data_in,data_out, status,we_data,we_command,command,scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );
 
    
    input        clk;     // master clock input
    input        rst;    
    input        i2c_rst;       
    
    input  [7:0] data_in;     // databus input
    output [7:0] data_out;     // databus output
    input        we_data;      // write enable input
    input        we_command;     // stobe/core select signal
    input  [4:0] command;     // valid bus cycle input
    output [3:0] status;
    
 
    reg [7:0] data_out;
 
    // I2C signals
    // i2c clock line
    input  scl_pad_i;       // SCL-line input
    output scl_pad_o;       // SCL-line output (always 1'b0)
    output scl_padoen_o;    // SCL-line output enable (active low)
 
    // i2c data line
    input  sda_pad_i;       // SDA-line input
    output sda_pad_o;       // SDA-line output (always 1'b0)
    output sda_padoen_o;    // SDA-line output enable (active low)
 
 
    //
    // variable declarations
    //
 
    // registers
    wire  [15:0] prer; // clock prescale register
    reg  [ 7:0] txr;  // transmit register
    wire [ 7:0] rxr;  // receive register
    reg  [ 4:0] cr;   // command register
    wire [ 3:0] sr;   // status register
 
    // done signal: command completed, clear command register
    wire done;
 
    // core enable signal
    wire core_en;
    wire ien;
 
    // status register signals
    wire irxack;
    reg  rxack;       
    reg  tip;        
    wire i2c_busy;   
    wire i2c_al;      
    reg  al;         
 
    
 
// generate data register
    always @(posedge clk or negedge rst)
      if (!rst)
        txr <= #1 8'h0;
      else if (i2c_rst)
        txr <= #1 8'h0;
      else if (we_data)
        begin
            
             txr <= #1 data_in;
        end
     
 
    // generate command register (special case)
    always @(posedge clk or negedge rst)
      if (!rst)
        cr <= #1 5'd0;
      else if (i2c_rst)
        cr <= #1 5'd0;
      else if (we_command)
        begin
            
              cr <= #1 command;
        end
      else
        begin
            if (done | i2c_al)           
            cr   <= #1 5'd0;            
        end
 
 
    // decode command register
    wire sta  = cr[4];
    wire sto  = cr[3];
    wire rd   = cr[2];
    wire wr   = cr[1];
    wire ack  = cr[0];
 
    wire nReset;
 
    assign nReset=rst;
 
    // decode control register
    assign core_en = 1;
    assign prer=16'h00c8;
    assign data_out=rxr;
 
 
    // hookup byte controller block
    i2c_master_byte_ctrl byte_controller (
        .clk      ( clk     ),
        .rst      ( i2c_rst ),
        .nReset   ( nReset),
        .ena      ( core_en      ),
        .clk_cnt  ( prer         ),
        .start    ( sta          ),
        .stop     ( sto          ),
        .read     ( rd           ),
        .write    ( wr           ),
        .ack_in   ( ack          ),
        .din      ( txr          ),
        .cmd_ack  ( done         ),
        .ack_out  ( irxack       ),
        .dout     ( rxr          ),
        .i2c_busy ( i2c_busy     ),
        .i2c_al   ( i2c_al       ),
        .scl_i    ( scl_pad_i    ),
        .scl_o    ( scl_pad_o    ),
        .scl_oen  ( scl_padoen_o ),
        .sda_i    ( sda_pad_i    ),
        .sda_o    ( sda_pad_o    ),
        .sda_oen  ( sda_padoen_o )
    );
 
    // status register block + interrupt request signal
    always @(posedge clk or negedge rst)
      if (!rst)
        begin
            al       <= #1 1'b0;
            rxack    <= #1 1'b0;
            tip      <= #1 1'b0;
           
        end
      else if (i2c_rst)
        begin
            al       <= #1 1'b0;
            rxack    <= #1 1'b0;
            tip      <= #1 1'b0;
           
        end
      else
        begin
            al       <= #1 i2c_al | (al & ~sta);
            rxack    <= #1 irxack;
            tip      <= #1 (rd | wr);
            
        end
 
    
    // assign status register bits
    assign sr[3]   = rxack;
    assign sr[2]   = i2c_busy;
    assign sr[1]   = al;    
    assign sr[0]   = tip;
    
assign status=sr;
endmodule

---

*******************************

 

[sudhirkv]

The code is perfectly working no issues on that.

How u r debugging your code. How do u say that u r not getting any output

Added after 7 minutes:

Ok make it like this.

first send the address of the eeprom and check whether u r getting the ack from the eeprom this will prove that the core is working fine.

If u have a oscilloscope probe the scl and sda line if the ack from the serial eeprom is coming then the design is working fine.

If u can explain me in block diagram then it will be easy to come to a conclusion.

I didnt have any issues in using the core.

Moreover u can use the wishbone interface which will make ur design more simpler.

Try running the scl in 100khz first then we can go for higher freq.

You can hardcode the divider value in the clock generation unit so that it will run in 100khz.

 

[naz56]

like this in xilinx after mapping pins of fpga with chip and displaying DOUT to 7 segment...

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module    test_i2c(sda,scl,clk,rst);
inout sda;
output scl; 
input clk,rst;
 
    
    wire        i2c_rst;       // asynchronous reset
    
    wire  [7:0] din;     // databus input
    wire  [7:0] dout;     // databus output
    wire       we_data;      // write enable input
    wire        we_command;     // stobe/core select signal
    wire   [4:0] command;     // valid bus cycle input
    
    wire ack;
    
wire sda0_o, sda0_oen;
wire sda, sda0_o, sda0_oen;
 
 
wire [7:0] dout;
 
fsm cmd_controller  cr (clk,rst,we_command,we_data,din,command,status);
 
i2c_master_top   core(.clk(clk), 
        .rst(rst), 
        .i2c_rst(1'b0),
        .data_in(din),
        .data_out(dout) ,
        .we_data(we_data),
        .we_command(we_command),
        .command(command),
        
        .scl_pad_i(scl),
        .scl_pad_o(scl0_o),
        .scl_padoen_o(scl0_oen),
        .sda_pad_i(sda),
        .sda_pad_o(sda0_o),
        .sda_padoen_o(sda0_oen)
        );
 
endmodule
***************
module fsm_cmd_controller (clk,rst,we_command,we_data,din,command,status);
 
input  [3:0]status;
output we_command;
output we_data
output [7:0]din
output [4:0]command
 
//fsm will be here
 
 
 
////
endmodule

---

****************************

 

[tushar365]

hi naz56 ,

I am in same scenario as you were.I want to communicate with AT24C04 EEPROM chip using FPGA.
can you please let me know was above code working? If yes can you please provide me working code for the same with state machine implementation.

Thanks in Advance.

 

[saurabhbhavsar19]

Ya i have used.

Any problem

hii
this is saurabh.
I m implementing I2C bus in VHDL.i downloaded code from opencores.org.
i m interfacing fpga with 8051 microcontroller to control internal registers and connected DAC (MCP4725) as slave.
plz help me about how to write data to DAC.what input i should give to scl_pad_i and and sda_pad i ?
plz plz plz help me out..

 

[mrflibble]

Does that i2c core have a wishbone bus? If yes, then you can use that. Plus I seem to recall that it had reasonable documentation, so you might want to look at that for some inspiration.

Short version: use the wishbone bus to write to internal registers of the core. With that you can write data to the DAC.

 

[saurabhbhavsar19]

instead of wishbone i m using 8051 to write internal registers.and i am not getting what clock frequency i should give to scl_pad_i.
I m transmitting data to FPGA by writing it on 'transmit register' using PIC programming in 8051, so i am confused what is input for sda_pad_i?
plz tell me what is sequential procedure to write data ?

---------- Post added at 09:29 ---------- Previous post was at 09:28 ----------

Thanks for reply!!!
instead of wishbone i m using 8051 to write internal registers.and i am not getting what clock frequency i should give to scl_pad_i.
I m transmitting data to FPGA by writing it on 'transmit register' using PIC programming in 8051, so i am confused what is input for sda_pad_i?
plz tell me what is sequential procedure to write data ?

 

[mrflibble]

I don't quite follow. You have 3 devices. A PIC microcontroller, an fpga and a DAC, yes?

What is connected to what?

You have the PIC connected to the fpga using what kind of bus? I2c?

You mentioned a DAC, how (as in bus, protocol) is that connected to what (fpga or pic)?

 

[saurabhbhavsar19]

I don't quite follow. You have 3 devices. A PIC microcontroller, an fpga and a DAC, yes?

What is connected to what?

You have the PIC connected to the fpga using what kind of bus? I2c?

You mentioned a DAC, how (as in bus, protocol) is that connected to what (fpga or pic)?

PIC microcontroller is connected to FPGA.It is used to control internal registers.
'wc_clk_i,wc_addr_i(3 bit),wc_data_i,wc_data_o,wc_rst_i' these inputs I've got from PIC microcontroller.
DAC is slave device which is connected to output pins of FPGA (scl_pad_o and sda_pad_o).