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Well, of course your friends Mr. Googlez and Ms. Wiki would
have plenty to tell you about it.
"Antenna effect" refers to plasma damage during processing.
A localized charging and gate current is imposed by dry etch
(positive charged ions) which can cause reliability degradation,
develop mismatch beyond the natural process scatter, or outright
rupture a gate deep in the guts (unlike pin applied ESD which
usually just hammers the I/Os).
The periphery of a metal layer determines the "aggressor"
charge / current. So long skinny lines and large area (hence
large periphery) are the threat sources.
The area of attached gate oxide (along with the population
of defects) determines how that current will be concentrated,
what current can be withstood. Gate oxides leak some, with
no impact (esp. newer nodes where gate tunneling is a major
thing anyway). More current can only be taken by voltage rise
and oxide rupture eventually, hot carrier damage leading up
to it. More oxide area tolerates more current so tolerates more
attached metal periphery.
An antenna feature "exercises" everything that is attached to it
from below. The stuff above, hasn't happened yet. So one key
mitigation is to break low level traces often and jumper them
with a higher level segment and vias. Floating segments do
nothing. Short connected-to-gate segments do nothing. You
would be better off with 5 1000um met1 segments with 4
2um jumpers connecting them, than 1 5000um met1 trace.
A last-ditch remedy is the "antenna diode" which can be
added to a line to ensure that there is an ohmic path to the
substrate, draining charge as it comes in. Not practical on
SOI (no chuck / substrate access) but common in JI digital
technologies.
hello dick_freebird,
thanks for your response, is "antenna diode" is same as pn diode or else is it different?. i didnt have any practical idea about this diode insertion (how to place in layout when antenna occur) can you show any pictorial representation of it, if possible
Hello all,
I am working on FM Radio transmitter to transmit at a range of 2km . I have constructed the circuit without testing because I am to connect a transmitting antenna to power on the circuit. I am thinking of using a dipole antenna with a frequency of 105.2MZ . I would be much appreciative for any advice on how to go about designing the antenna will be of great help.
Regards
sheriff
Antenna diode is often just a lonely N+ contact placed in the Psub
at a place of convenience in the Met1 trace that's flagging. It has
no purpose other than bleeding charge so is wanted to be as small
and simple as possible.
The antenna current may be applied to a source or drain, but in
general these serve as "freebie" antenna diodes, lit up (in the
sense of photoconduction) by the same plasma etch's soft
X-rays, so effective at in-situ charge bleeding. This is why an
antenna rules check often focuses on nets which are not (yet)
attached to a junction.
Not to say you couldn't design a layout stupid enough to be a
problem. But you'd have to try harder than normal. And in
general a S/D junction will break over well before an oxide
even if it's not photoconducting like mad.
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