Analog design in 90nm process

[derekqiao]

Do u have any experiences at analog design in 90nm such as opamp, bandgap, comparator?
In my hspice simulation results, the gate of MOS has current. Is it right, or the spice model is wrong?

 

[Humungus]

At 90nm, tunneling through the gate oxide is very high, that is why your model includes the gate current. Hard to manage it, isn't it?

 

[derekqiao]

It is difficult to consider this leakage current. Such as in bandgap, i designed a NMOS to work as cap, but the gate current would damage the performance of bandgap.
Could we simulate this leakage current exactly?

 

[yibinhsieh]

derekqiao wrote

It is difficult to consider this leakage current. Such as in bandgap, i designed a NMOS to work as cap, but the gate current would damage the performance of bandgap.
Could we simulate this leakage current exactly?

Yes, the founday has predicted and modeled the gate leakage in the model file.

If you want to use the MOS as capacitor, try to use I/O device.

Yibin.

 

[Yun Lin]

You must consider MIM capacitor for some big capacitor design. The leakage of gate and source_drain is challenge.

 

[tecsiun]

It is normal that the gate of MOS has current because of the leakage current from gate to substrate for low-k .

Added after 6 minutes:

It is the challenge for the 90nm age.