I think that somehow desing process of analog ckts is similar to that of software. The schematic is sortof seen as the code. Below I take an example of design w/ Cadence.
If I design a big ckt, first I divide the whole one into a few seperate blocks.
Second, I begin to work on each individual block, I use design parameter to take place of the real device parameter (width, length, ...) to save some efforts. After some simulation routine (sweep, plot, ...), the individual block is verified and then I save the "design state" in ADE of Cadence. Then I establish symbol for this block.
Third, After I finish the design for all of the inidividual blocks, I will hook up these blocks/symbols together. So it comes to the simulation/verification of whole systems.
If the big ckt is not that much, I'm OK with my design process. Otherwise, I might have to handle with tens of design parameters as coming to the step of systems simulation, since I save the design state/parameters for each block. Sometimes, It's really messed up. I wonder if I should change my methdology about the process. So could you smarties share your golden methodology with me here? I really appreciate it! Thx.