Addition of a signed and an unsigned number

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but y isn't it working here.. am doing my project work on this xilinx and I have to link a fpga to it.. how to get correct output here??
 

Instead of this:
particleynamics said:
module adder(result,operand1,operand2);
input signed [31:0]operand1;
input [15:0]operand2;
output signed [31:0]result;
reg signed [31:0] result;
always @(operand1,operand2)
begin
result = operand2 + operand1;
end
endmodule
Click to expand...

Try this:
Code: 
module adder(result, operand1, operand2);
   input  signed [31:0] operand1;
   input         [15:0] operand2;
   output signed [31:0] result;
   reg    signed [31:0] [COLOR="#FF0000"]interim2[/COLOR];

   always @(operand1, operand2)
   begin
      [COLOR="#FF0000"]interim2 = $signed(operand2);[/COLOR]
      result   = operand1 + [COLOR="#FF0000"]interim2[/COLOR];
   end
endmodule
 
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