Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Addition of a signed and an unsigned number

Status
Not open for further replies.
but y isn't it working here.. am doing my project work on this xilinx and I have to link a fpga to it.. how to get correct output here?? :(
 

Instead of this:
module adder(result,operand1,operand2);
input signed [31:0]operand1;
input [15:0]operand2;
output signed [31:0]result;
reg signed [31:0] result;
always @(operand1,operand2)
begin
result = operand2 + operand1;
end
endmodule

Try this:
Code:
module adder(result, operand1, operand2);
   input  signed [31:0] operand1;
   input         [15:0] operand2;
   output signed [31:0] result;
   reg    signed [31:0] [COLOR="#FF0000"]interim2[/COLOR];

   always @(operand1, operand2)
   begin
      [COLOR="#FF0000"]interim2 = $signed(operand2);[/COLOR]
      result   = operand1 + [COLOR="#FF0000"]interim2[/COLOR];
   end
endmodule
 
Last edited:

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top