Addition of a signed and an unsigned number

particleynamics · Apr 18, 2012

I am trying to add a signed and an unsigned number in verilog. Can someone tell me how to??
Am not able to do..

kornukhin · Apr 18, 2012

Use 'signed' / 'unsigned' keyword.

ex.:

wire signed [7:0] a;

particleynamics · Apr 18, 2012

I meant I hv to add a signe number with an unsigned..
for example 20 + 10, 20 + (-10), 20 + (-30)
Basically an adder subtractor block where 1 input is signed and the othe unsigned. How do I do it??

kornukhin · Apr 20, 2012

20+10, 20+(-10), 20+(-30)
all of this numbers are unsigned. To specify them as signed use
6'sd20+6'sd10
6'sd20+(-6'sd10)
6'sd20+(-6'sd30)
In this case result of operation will be signed.

dave_59 · Apr 20, 2012

In Verilog, all operands must be signed for the result to be signed, otherwise the result will be unsigned. All arithmetic is 2-complement. The only difference between signed and unsigned is how relational operators work and how smaller width signed values are sign extended into larger width signed values. If the the width of a signed operand is smaller than the unsigned operand in the same expression, it's up to you to sign extend the smaller operand.

particleynamics · Apr 24, 2012

actually I on't want the output in the form of 32758 for -10 as output , I want it as -10 if I have done 20-30. How to implement this??
thanx fr ur responses.. plz hlp me solve this problms. I will attach test bench if u want.

shanmugaveld · Apr 24, 2012

check below pdf to work on signed and unsigned in verilog.

**broken link removed**

particleynamics · Apr 24, 2012

This is the snapshot I am getting.. I want the results as -10, 0 etc etc..

dave_59 · Apr 24, 2012

You need to understand the widths of signed numbers versus unsigned. You appear to be working with all 16-bit numbers. If the first operand is 16-bit unsigned and the second is 16-bit signed, how do want the result of 16'hFFFF + 0 to be represented? You either need to reduce the first operand to 15 bits, or maker the result 17-bit signed.

particleynamics · Apr 25, 2012

our unsigned number is 16 bits in range (it is nvr never going to have a negative value) while the other number is signed n of 30 bits in length.. we want to add or subtract depending on the sign of the signed number.. Can u please write a code on how to do it?? thanx fr d help

dave_59 · Apr 25, 2012

Code:

reg signed [31:0] result;
reg signed [31:0] operand1;
reg [15:0] operand2;

always [...] begin
    ...
    result = operand1 + operand2;
    ...
end

particleynamics · Apr 26, 2012

I tried the code given.. It is just adding the two giving a negative sign.. Can u pls solve this?? It has been so many days and u people couldn't solve 1 problem!!

---------- Post added at 17:21 ---------- Previous post was at 17:20 ----------

It should add or subtract depending upon the sign of the signed number.. thats what I have been asking for.. can't u people give solution for this???

godfreyl · Apr 26, 2012

I think you need to convert the unsigned number to a signed number first, then add it to the other (signed) number.

particleynamics · Apr 26, 2012

n how to do that?? can u help me with a code??

godfreyl · Apr 26, 2012

Geez, you're asking me? I never even heard of verilog before I looked in this thread!

Let's give it a bash anyway. The PDF linked to in post 7 explains how to do type casting. Apparently you have to use the $signed operator, so:

Let's say you have an unsigned number A, and a signed number B.
First declare another signed number C.
Then use this code:

Code:

C = $signed(A)

Then add B and C.

dave_59 · Apr 26, 2012

particleynamics,

You need to show the code you are running. It either has a bug, or the simulator you are using has a bug. I just tried this with modelsim

Code:

module top;
   reg signed [31:0] operand1;
   reg [15:0] 	     operand2;
   reg signed [31:0] result;

   initial begin
      operand1 = -1;
      operand2 = 10;
      result = operand1 + operand2;
      $display(result,,operand1,, operand2);
   end
endmodule

and the result I get is

Code:

#           9          -1    10

particleynamics · Apr 26, 2012

Dave_59 am using XILINX... n the code goes as follows ..

Pls helpme..
module adder(result,operand1,operand2);
input signed [31:0]operand1;
input [15:0]operand2;
output signed [31:0]result;
reg signed [31:0] result;
always @(operand1,operand2)
begin
result = operand2 + operand1;
end
endmodule

dave_59 · Apr 26, 2012

need your complete testbench

particleynamics · Apr 26, 2012

i manually assign random values in the testbench.. don't hv a program for it...

dave_59 · Apr 26, 2012

There is no problem with your code. it the way your simulator is displaying values of the top level. This works for me.

Code:

module adder(
   input wire signed [31:0] operand1,
   input wire [15:0] 	     operand2,
   output reg signed [31:0] result
	     );
   
   always @(operand1 or operand2)
      result = operand1 + operand2;
endmodule

module top;
   reg signed [31:0] op1;
   reg [15:0] 	     op2;
   wire signed [31:0] result;

   adder a1(op1,op2,result);

   initial begin
      op1 = -1;
      op2 = 10;
      #10
	$display(result,,op1,,op2);
   end
endmodule

Addition of a signed and an unsigned number

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