vGoodtimes
Advanced Member level 4
Code:
-- buffer is 128b for convenience
-- not sure if this synthesizes, if not just use a different mux
-- construct.
process (clk) is
variable nextStateExt : integer range 0 to 31 := 0;
variable nextState : integer range 0 to 15 := 0;
begin
if rising_edge(clk) then
nextStateExt := validIn + state; -- validIn is assumed to be integer range 0 to 16
nextState := nextStateExt mod 16;
-- lsbs will be buffer, msbs will be dataIn
dataOut <= buffer;
dataOut(127 downto 8*state) <= dataIn(127 - 8*state downto 0);
if (nextStateExt >= 16) then
validOut <= '1';
else
validOut <= '0';
end if;
if (nextStateExt >= 16) then
-- copy the msbs of data in to the lsbs of buffer
buffer(127 - 8*state downto 0) <= dataIn(127 downto 8*state);
else
-- copy the lsbs of data to the msbs of buffer
buffer(127 downto 8*state) <= dataIn(127 - 8*state downto 0);
end if;
// and update state
state <= nextState;
end if;
end process;
This should be the packer. Not sure if the mux is supported like that in quartus. You should probably double check it for errors as I threw it together quickly.