Accessing records in VHDL

type type_variable_size_word is
record
  one_byte_word : std_logic_vector ( 1 * 8 - 1 downto 0 ) ;
  two_byte_word : std_logic_vector ( 2 * 8 - 1 downto 0 ) ;
  three_byte_word : std_logic_vector ( 3 * 8 - 1 downto 0 ) ;
  four_byte_word : std_logic_vector ( 4 * 8 - 1 downto 0 ) ;
end record ;

signal variable_size_word  : type_variable_size_word ;

signal a : std_logic_vector ( 1 * 8 - 1 downto 0 ) ;
signal b : std_logic_vector ( 2 * 8 - 1 downto 0 ) ;
signal c : std_logic_vector ( 3 * 8 - 1 downto 0 ) ;
signal d : std_logic_vector ( 4 * 8 - 1 downto 0 ) ;

signal variable_size_word:  type_variable_size_word;

-- One way
variable_size_word.one_byte_word  <= a;
variable_size_word.two_byte_word <= b;
variable_size_word.three_byte_word <= c;
variable_size_word.four_byte_word  <= d;

-- Another way
variable_size_word <=
(
    one_byte_word  => a,
    two_byte_word => b,
    three_byte_word => c,
    four_byte_word  => d
);

one_byte_word : std_logic_vector ( 1 * 8 - 1 downto 0 ) ;
two_byte_word : std_logic_vector ( 2 * 8 - 1 downto 0 ) ;
.
.
.
hundred_byte_word : std_logic_vector ( 100 * 8 - 1 downto 0 ) ;

type type_variable_size_word is
record
  iterative_record_declaration : for index in 1 to 100 
  generate
      x_byte_word : std_logic_vector ( index * 8 - 1 downto 0 ) ;
  end generate ;
end record ;

Ex1 : for index in 1 to 100 generate
    signal x_byte_word : std_logic_vector ( index * 8 - 1 downto 0 ) ;
begin
    ....
    -- Here you can access only the 'x_byte_word' that corresponds with the single value
    -- of 'index'.  There would be no visibility to the 'x_byte_word' that goes along with any 
    -- other value of index.
end generate Ex1;

type t_Ex2 is record
    Value: integer; -- Will limit you though to the size of a VHDL integer, 31 bits
    Sizeof: positive;
end record t_Ex2;
type arr_t_Ex2 is array(natural range<>) of t_Ex2;
signal My_Sig:  arr_t_Ex2(1 to 100);
-- Now you have complete access to any of the 100 values.  They can be cast into
-- std_logic_vectors like this...

some_slv <= std_logic_vector(to_unsigned(My_Sig(i).Value, My_Sig(i).Sizeof));

number_of_valid_symbols <= number_of_symbols - empty ;

generate_enable_vector : for index in 1 to number_of_symbols 
generate
  if number_of_valid_symbols >= index then 
    enable_vector ( index ) <= '1' ;
  else
    enable_vector ( index ) <= '0' ;
  end if ;	
end generate generate_enable_vector ;

record DataBus is
  data : std_logic_vector;
  en : std_logic;
end record;

number_of_valid_symbols <= number_of_symbols - empty ;

process ( clock ) is
begin 
   if rising_edge ( clock ) then
      if valid = '1' then
         whole_message ( ( pointer + number_of_valid_symbols * symbol_size - 1 ) downto pointer <= incoming_message ( number_of_valid_symbols * symbol_size - 1 downto 0 ) ;
         pointer <= pointer + number_of_valid_symbols * symbol_size ;
      end if ;
   end if ;	
end process ;

current_valid_symbols <= total_symbols - empty ;

process ( clock ) is
begin 
  if rising_edge ( clock ) then
    if valid = '1' and current_valid_symbols  > 1 then
      big_message ( ( pointer + current_valid_symbols * 8 - 1 ) downto pointer ) <= message ( current_valid_symbols  * 8 - 1 downto 0 ) ;
      pointer <= pointer + current_valid_symbols * 8 ;
    end if ;
  end if ;	
end process ;

constant MAX_SYMBOLS: natural := 16;
signal Next_Symbol: natural range 0 to (MAX_SYMBOLS-1); -- The range of symbols
signal empty:  natural range 0 to (MAX_SYMBOLS-1); -- From Avalon
constant BITS_PER_SYMBOL: natural := 8;
signal Data_In:  std_ulogic_vector((BITS_PER_SYMBOL-1) downto 0); -- From Avalon
constant MSGS_PER_BIG_MSG: natural := 100; -- What you had stated
signal My_Big_Msg:  std_ulogic_vector(BITS_PER_SYMBOL*MAX_SYMBOLS*MSGS_PER_BIG_MSG-1 downto 0);
...
process(clock)
begin
    if rising_edge(clock) then
        if (Some_Form_Of_Reset = '1') then
            Next_Symbol <= 0;
        elsif (valid = '1') then
            [COLOR=#ff0000]if (TBD) then -- How to handle wrapping needs to be decided[/COLOR]
                Next_Symbol <= 0;
            else
                Next_Symbol <= Next_Symbol + MAX_SYMBOLS-1-empty;
            end if;
        end if;

        for i in 0 to (MSGS_PER_BIG_MSG-1) loop
            if (Next_Symbol >= i) then -- KJ:  Essentially creates the enable signal here
                for i in Data_In'range loop
                    My_Big_Message(BITS_PER_SYMBOL * i) <= Data_In(i);
                end loop;
           end if;
        end loop;
    end if;
end process;