I wonder if we may face a simple case of an inappropriate tolerance parameter for the DC bias point solver, causing inplausible operation conditions for an individual part, not visible in the output bias voltage?
I encountered a strange thing when analyzing the opamp's AC characteristic, that the AC phase plot start from -180 degree at DC frequency, and begin to increase to -170, -160... etc.
And the pz analysis showes there is a RHP pole.
But when decrease the supply voltage, the AC plot returns to normal.
The OP amp's circuit has been proved on other process, and i just want to migrate it to another process.
Any one meet the similar thing?
Dear Walk4567,I got the same problem in my class AB opamp in GRACE 1.8/12V device process.I want to know: Have you sloved this problem or got some conclusion of this problem?
Thanks!
As for why... I still don't know for sure but I am 90% sure its just a bug in the model.. and never mind its just an AC response, which you can not trust 100% ever! The true way to see if everything is ok is doing a transient response the way the amplifier will be made. As you can see if my form above, my tran responses all good great so i taped out the chip and it functions 100% in silicon with no crazy amplifiers! I would say just ignore it and check your transient!
Hope this helps
Jgk
As for why... I still don't know for sure but I am 90% sure its just a bug in the model.. and never mind its just an AC response, which you can not trust 100% ever! The true way to see if everything is ok is doing a transient response the way the amplifier will be made. As you can see if my form above, my tran responses all good great so i taped out the chip and it functions 100% in silicon with no crazy amplifiers! I would say just ignore it and check your transient!
Hope this helps
Jgk
It also happens with the inductor as well. Like all the other posts say, its not a correct DC biasing since all the .op result are about the same DC points for all nodes... It happens with all AC simulations... Its just you don't see it all the time. I only saw it after 200 monte carlo runs on one amplifier and about 1000 runs on a different one.... My models were TSMC 90nm... Just do a transient in how your amplifier will be used and see if its stable.
Jgk
I think this is a bug of spectre AC analysis.
When your DC OP of INN is higher than INP , the AC phase curve will present -180 at low freq.
Improve your DC feedback circuit, and let the INP always higher than INN will be okay.
Good luck!
I encountered a strange thing when analyzing the opamp's AC characteristic, that the AC phase plot start from -180 degree at DC frequency, and begin to increase to -170, -160... etc.
And the pz analysis showes there is a RHP pole.
But when decrease the supply voltage, the AC plot returns to normal.
The OP amp's circuit has been proved on other process, and i just want to migrate it to another process.
Any one meet the similar thing?
I observed this kind of phenomenon in some of my designs of Opamps.. i realised it is always due to multiple feedback paths created by the circuits at the first stage outputs(maily due to circuits designed for biasing the pushpull stages). so i expect some problem in the pushpull biasing circuits please check there
It may be inappropriate to write this old thread but I believe it is important. I met this case also and I think it has something to do with impact ionization or some models. Try connecting bulks of cascoding FETs to their sources. Keep in mind that in twin well processes you are allowed to connect the bulk of nmos transistors to somewhere else than ground. If this solves your problem please reply, I would like to know if this is a general case.