AC phase shift 180 degree

[ict_eda]

Hi walker,

By bias voltages I mean the dc operating voltages inside the op-amp.

ict_eda

 

[Wu_uW]

Hi walker5678:

sorry I can not answer your question. ;-)

but I have a naive one to learn this opamp: what is the usage for the caps between the two biasing gate?

 

[walker5678]

That's just for stabilizing the biasing point. The circuit does not show the detail: the common terminal of the two capacitors is gnd.

 

[walker5678]

I wonder if we may face a simple case of an inappropriate tolerance parameter for the DC bias point solver, causing inplausible operation conditions for an individual part, not visible in the output bias voltage?

Hi, FvM

Do you know what tolerance or other options will affect the AC phase simulation result?

Thanks.

 

[hbchens]

Re: op amp dc bias phase shift

I encountered a strange thing when analyzing the opamp's AC characteristic, that the AC phase plot start from -180 degree at DC frequency, and begin to increase to -170, -160... etc.
And the pz analysis showes there is a RHP pole.
But when decrease the supply voltage, the AC plot returns to normal.
The OP amp's circuit has been proved on other process, and i just want to migrate it to another process.
Any one meet the similar thing?

Thanks

Dear Walk4567,I got the same problem in my class AB opamp in GRACE 1.8/12V device process.I want to know: Have you sloved this problem or got some conclusion of this problem?
Thanks!

 

[jgk2004]

I had the same problem last year as well. See below in this link

https://www.edaboard.com/threads/166558/

As for why... I still don't know for sure but I am 90% sure its just a bug in the model.. and never mind its just an AC response, which you can not trust 100% ever! The true way to see if everything is ok is doing a transient response the way the amplifier will be made. As you can see if my form above, my tran responses all good great so i taped out the chip and it functions 100% in silicon with no crazy amplifiers! I would say just ignore it and check your transient!
Hope this helps
Jgk

 

[hbchens]

I had the same problem last year as well. See below in this link

https://www.edaboard.com/threads/166558/

As for why... I still don't know for sure but I am 90% sure its just a bug in the model.. and never mind its just an AC response, which you can not trust 100% ever! The true way to see if everything is ok is doing a transient response the way the amplifier will be made. As you can see if my form above, my tran responses all good great so i taped out the chip and it functions 100% in silicon with no crazy amplifiers! I would say just ignore it and check your transient!
Hope this helps
Jgk

Dear JGK:
Thanks for your help.Could you tell me which model you have used when you find this problem?

 

[tiger888]

Re: op amp dc bias phase shift

I think R0 of your testbench should be replaced by inductor (ind).
It would be difficult to get the correct DC bias with so large feedback resistor.

 

[jgk2004]

It also happens with the inductor as well. Like all the other posts say, its not a correct DC biasing since all the .op result are about the same DC points for all nodes... It happens with all AC simulations... Its just you don't see it all the time. I only saw it after 200 monte carlo runs on one amplifier and about 1000 runs on a different one.... My models were TSMC 90nm... Just do a transient in how your amplifier will be used and see if its stable.
Jgk

 

[Alan.Zhu]

I think this is a bug of spectre AC analysis.
When your DC OP of INN is higher than INP , the AC phase curve will present -180 at low freq.
Improve your DC feedback circuit, and let the INP always higher than INN will be okay.
Good luck!

 

[rajanarender_suram]

Re: op amp dc bias phase shift

I encountered a strange thing when analyzing the opamp's AC characteristic, that the AC phase plot start from -180 degree at DC frequency, and begin to increase to -170, -160... etc.
And the pz analysis showes there is a RHP pole.
But when decrease the supply voltage, the AC plot returns to normal.
The OP amp's circuit has been proved on other process, and i just want to migrate it to another process.
Any one meet the similar thing?

Thanks

Hi Walker ..

I observed this kind of phenomenon in some of my designs of Opamps.. i realised it is always due to multiple feedback paths created by the circuits at the first stage outputs(maily due to circuits designed for biasing the pushpull stages). so i expect some problem in the pushpull biasing circuits please check there

 

[rajanarender_suram]

or either u have not sized the output transistors properly

 

[rocket_wang]

hi, walker have you solved the question? i meet the case also. tran sim is ok.
you said , there maybe nagetive ac res, have confirm it yet? \

 

[tanguaner]

hi, walker have you solved the question? i meet the case also. tran sim is ok.
Is this a soft bug?

 

[kemiyun]

It may be inappropriate to write this old thread but I believe it is important. I met this case also and I think it has something to do with impact ionization or some models. Try connecting bulks of cascoding FETs to their sources. Keep in mind that in twin well processes you are allowed to connect the bulk of nmos transistors to somewhere else than ground. If this solves your problem please reply, I would like to know if this is a general case.

Thanks
Orhun

 

[hsh22]

make sure the circuit and the formula is correct at first
it's complex，i have not touched the R2R structure