About Pre-amp Cgd's Effects in SAR ADCs

[SafeIC]

Suppose the CDAC output is connected to a pre-amp. During bit-cycling of a SAR ADC, the charge stored in Cgd of the pre-amp's input pairs varies. This may cause dynamic error on the residue voltage. Can this effect be treated as "kickback" as well? I have found that in some papers they mentioned adding pre-amp can deal with the kickback from the latch. However, I think pre-amp still cause dynamic error as mentioned. Could anybody help me with this, thank you very much!!

 

[dick_freebird]

This is just settling time and Cload. If preamp input C is below spec condition then it's all good. As long as your lineup respects settling time in DAC and amp all told.

 

[SafeIC]

This is just settling time and Cload. If preamp input C is below spec condition then it's all good. As long as your lineup respects settling time in DAC and amp all told.

Thanks for your answer! I agree that the settling error can be minimized, but here I mainly mean the static error. To my understanding, Cload you mentioned refers to the equivalent input C contributed by miller capacitance Cgd. This capacitance is not fixed during SAR conversion, especially at the first several bit cycles when the input pair of the pre-amp works in highly non-linear region. Therefore, bit-weight changes during SAR conversion. Does this lead to static error?

Another question is, why this Cgd largely increases the settling time of Vres? I found that for the MSB cycle, even if all the bit-capacitors' bottom plates have settled within +-0.5 LSB, Vres is still far away from settled. Any suggestion would be appreciated!

 

[dick_freebird]

Direct Miller gain applies to Cdg while bit caps I expect are low-Z to somewhere, baggage but no entourage.

Conservative design of any buffer might add excess.

 

[SafeIC]

Another question: It seems the cases are a bit different when the kickback-sensitive node is driven by active components or passive components. If the output node of an opamp is connected to the latch input, then any kickback only causes dymamic transients without affecting the DC point. However, it the output node of the CDAC is connected to the latch, kickback causes both dynamic error and a voltage droop (static error).

In SAR ADC, if Vres causes kickback error -αVres and α is always smaller than 1, then it means the decision would not be affected. If this can be ensured, is it true that kickback has no negative effects to the ADC? Thank you!!!

 

[nitishn5]

Late to the party but nonetheless...

One thing you have to be concerned about is that the Cgd of the pre-amp or the latch is non-linear. It will vary with the different voltage for each bit conversion cycle.
The Cgd being parallel to the CDAC will cause a scaling error.
And this scaling error can be non-linear.
And depending on the number of bits and the Total CDAC capacitance, the non-linearity can be significant and can affect your DNL/INL.

 

[SafeIC]

Late to the party but nonetheless...

One thing you have to be concerned about is that the Cgd of the pre-amp or the latch is non-linear. It will vary with the different voltage for each bit conversion cycle.
The Cgd being parallel to the CDAC will cause a scaling error.
And this scaling error can be non-linear.
And depending on the number of bits and the Total CDAC capacitance, the non-linearity can be significant and can affect your DNL/INL.

Thank you for your suggestions! By the way, do you have any advice on Floor #5's questions?

 

[D.A.(Tony)Stewart]

Ceramic high Dk caps have a memory or kickback effect. But not C0G types.