huashizng
Newbie level 6
![Newbie level 6](/styles/images/ranks/blevel3.gif)
now I am designing a small LDO circuit, which is used to provides power supply to low voltage blocks in the chip. In this LDO circuit, power supply ranges from 6v---25v. the output voltage is 5.7v. the output voltage's tolerance may be 10%. the output stage is PMOS common source structure.if power supply>6.5v, the gain can reach 70db. when supply is 6v, because Vds of the regulator is very small, so it will operate in the linear region. at this time, the loop gain is very smll,for example -100db. but the output voltage is ok( still larger than 5.3v). what's the shortcoming? I don't know whether I can use this circuit???
because the size of the regulator transistor is large, i don't want to continue to increase the size. there is a outer 10u capacitor connected the ouput of LDO.
because the size of the regulator transistor is large, i don't want to continue to increase the size. there is a outer 10u capacitor connected the ouput of LDO.