90 degree phase shifter for a sine wave with variable frequency

[newbie_hs]

I need to design 90 degree phase shifter for a sine wave of amplitude 1V and frequency varies from 5Khz to 50Khz I found some solutions here itself.
In all those approaches amplitude varies with frequency.

I need constant amplitude at all these frequency range.May I know any circuit ideas.

 

[mtwieg]

Sine wave comes from Function generator.

Ok this changes everything.

Use a function generator with two outputs, and use it to directly generate the phase shifted output (with the frequency/amplitude of one output locked to the other). This is something that any decent function generator with multiple outputs should be capable of.

You'll get near perfect phase and amplitude, no need for any magic circuits externally.

edit: beaten by barry, I guess

 

[D.A.(Tony)Stewart]

They will probably say, we don't have one.
If you want help, say what you are trying to prove to avoid newbie errors from inadequate specs.

Quadrature encoders are trivial, external analog variable f fixed-phase shifters require what U lack and alternative solutions may exist.

 

[betwixt]

An alternative but it needs a little construction work is to use two DDS signal sources like the AD985x series, they are available very cheaply from many outlets. Then measure the input frequency and use it to program both DDS but tell one of them to shift phase (it is programmable) by 90 degrees. That gives you a theoretical range from almost DC to several MHz, 0, 90, 180 and 270 degree outputs as sine or square waves.

Very little cost but some software needed to measure and program the DDS modules.

Brian.

 

[FvM]

Tracking all-pass filter can basically achieve what you want

Brief desciption
- U1 forms programmable low-pass (gm-C filter)
- C3/R15 cancels DC offset
- U2 combines low-pass output with input signal forming an all-pass
- U3, U4 + XOR A1 measures phase shift, XOR output has 50 % duty cycle at 90 degree
- U5 integrates error signal
- R16/R4 reduces 2*f0 ripple that causes signal distortion at low signal frequencies
- control signal tunes low pass

Example waveform, settling for 10 kHz input:

 

[D.A.(Tony)Stewart]

Nice design Frank. Here are my 1% suggestions for improvements.

- Many resistors that affect gain. Choose 0.1% tolerance if possible , or adjust R4 accordingly.
- C3 has some AC voltage drop @ 5kHz can could be increased x10.
- V(ctrl) has enough ripple to cause +/-2% amplitude and phase error.
- modified & added LPF to support low f range.

 

[newbie_hs]

@FvM ,

Thank you very much.
This is the first time I am hearing 'Tracking all pass filter'.
I did a google search for some materials so that I can study.
Unfortunately did not find anything.If you can suggest some materials/books, it is well and good

 

[D.A.(Tony)Stewart]

@FvM ,

Unfortunately did not find anything.If you can suggest some materials/books, it is well and good

This is fundamentally a PLL design using XOR as the phase mixer with 2F and DC out.
The OTA variable R, fixed C as the analog phase shifter rather than a VCO.
The error amplifier is an integrator in most PLL's unless there is a critical stability or speed requirement for jitter, phase noise then more complex PID filters are used.

I added a 2nd order LPF to reduce the AM and PM effects of V(ctrl) ripple.
But that also reduces phase margin in the loop and introduces some sub- harmonic resonance that is hard to see with my values but depending on the amount of overkill on V(Ctrl) filtering that may be between 5% to 30% of the signal frequency and result in returning the AM/PM jitter in a repeating longer period than just 1/2f. Since the variable OTA resistance control the current in R7, changes the phase shift and amplitude, it also shifts the pole and the unity gain point where phase margin is measured. I did not attempt to optimize it with a Kd gain aka lead-lag compensation filter, as it appeared good enough after 100 ms startup and I know you were in no rush to switch frequencies. Frank's initial design you may judge as adequate, my changes are just small reductions in amplitude error.

I did try an FM sweep using 12.5 kHz carrier 100% modulation at 50 Hz to see the tracking and it looked good ( although only about 10kHz to 40 kHz) changing the non-linear FM parameters when swept too low below 5kHz could cause U5 to clip to -15V which means the loop gain suddenly becomes "zero". Then the 50 Hz sine V(ctrl) looks a but ragged swinging at the negative peak. Some adjustments may prevent this but a 1 decade span seems to be the limit for a single stage OTA in a dual chip unles you avoid overshoot with the PID optimization. But you are just static tuning, so no worries.

 

[FvM]

Thanks for improvements. Bottleneck is limited OTA performance, for larger frequency range I would consider precision analog multiplier. C3/R15 highpass doesn't affect circuit performance if I understand right, low pass path isn't required to realize a specific gain. High pass cancels frequency dependant OTA offset, increasing time constant also increases settling time.

I was thinking about a full featured SOGI (second order generalized integrator) FLL in the first place, it also uses a 90 degree detector for tracking control. We are using an all digital version of this filter for grid tied inverter reference signal generation. Then I found that simpler tuned all-pass already does the trick.

For reference, see SOGI-FLL diagram, copied from Theodoresco et al, Grid Converters for Photovoltaic and Wind Power Systems qv' is quadrature (90 degree) output

 

[D.A.(Tony)Stewart]

C3/R15 highpass only affects circuit performance by increasing output swing of V(ctrl) at fo, which is only reduces clipping margin at lowest f which drives the Darlington OTA.

 

[dick_freebird]

PLL and wave-DAC might be cleanest. You could
run two counters with (say) 00000000 and 11000000
start-count-loads and two PROMs, 2 DACs, badda-bing.

 

[BradtheRad]

In case you wish to explore analog waveform generators...
Link describes the Sulzer oscillator, which maintains a constant amplitude over a range of frequencies. One potentiometer is sufficient to vary frequencies. The circuit is a variation on all-pass network.

allaboutcircuits.com/technical-articles/oscillator-circuit-never-heard-of-the-sulzer-network/

Simulation of the oscillator shows two or more nodes staggered 90 degrees from one another. Success probably requires a lot of adjusting.

 

[BradtheRad]

Of course It's hard to beat the digital route. Amplitude and phase positioning are both versatile.
Cascade of D flip-flops energizes a weighted resistor network in the proper sequence. This simulation produces two waveforms by taking outputs at Q and bar-Q. Invert-gates introduce phase differences.

Amplitude and phase difference are fixed (theoretically) at all frequencies. To obtain 50kHz output, you must apply 800kHz clock. By adding DFF stages you can obtain better resolution.

--- Updated Monday at 5:37 AM ---

Link below runs schematic above using Falstad's animated interactive simulator.
Free to download and use.

tinyurl.com/2yt3vpy5

 

[newbie_hs]

Of course It's hard to beat the digital route. Amplitude and phase positioning are both versatile.
Cascade of D flip-flops energizes a weighted resistor network in the proper sequence. This simulation produces two waveforms by taking outputs at Q and bar-Q. Invert-gates introduce phase differences.

Amplitude and phase difference are fixed (theoretically) at all frequencies. To obtain 50kHz output, you must apply 800kHz clock. By adding DFF stages you can obtain better resolution.
View attachment 198627

--- Updated Monday at 5:37 AM ---

Link below runs schematic above using Falstad's animated interactive simulator.
Free to download and use.

tinyurl.com/2yt3vpy5

My input is a sine wave of frequency 5Khz to 50khz .At the output I need a 90 degree phase shifted version of this input.

 

[dick_freebird]

PLL w/ VCO can multiply and track the input clock,
for your divide-back-down wavetable index.
You can find interger-N PLLs that let you hard-strap
the divisor bits, making it "fairly not-needy".

 

[D.A.(Tony)Stewart]

The voltage-controlled current phase-shifting OTA approach (phase locked loop) has a stability advantage over the PLL w/ VCO because of the added 1/s integrator term of the VCO in the loop equation. This means the VCO tolerance must be within the capture range or a type II f/p digital mixer must be used which has some jitter sensitivity.

But either way works.

The only gotcha is the need for matched gain resistors or calibrated inverted analog signal.

 

[FvM]

We didn't yet hear dynamic requirements, expected df/dt, stepped or continuous frequency variation, necessary settling time.

The motivation behind post #44 was to demonstrate feasibility of a purely analog solution. All-digital PLL with DDS sine generation is state-of-the-art and would be probably used these days in most cases.

 

[danadakk]

One method. Single Chip, measure freq of sine and then program DDS, regenerate sine
and a 90 deg version if it, Drives wavedac clocks to create analog sine or square or both/wavedac.
Each wavedac has ability to select one of to waveforms, could be used for other timing. Again all
on one chip, many resources left for other tasks than whats shown.

Latency, because freq cntr is a reciprocal counter, just over 1 cycle.

Note use one of the onchip comparators to square up incoming sine for freq cntr....I did not show that.

Code, maybe no more than a dozen lines of code.