8 phases non-overlapping clock from johnson by 4 divider

[Anomis]

Hi EDA members,
I want to design a 8 phases non-overlapping circuit from johnson divider by 4 circuit. I already referred to this post for a hint:

https://www.edaboard.com/threads/4-phases-non-overlapping-clock-generator.342504/

But the thing is my clock input has constraints that I cannot make it as large as i want:
For example I have a source of fi=4 GHz and want 8 phases output signals with DCD = 12.5 % non-overlapping, f0=1GHz. The simple solution is just to use a divider by 8 circuit with fi=8GHz, then i have f0 = 1GHz with 8 phases as desired. However i don't have such big clock source of 8GHz. How can I solve this problem with this condition?
Very much appreciated your help!
Tommy

 

[Anomis]

@KlausST, I don't think this is being done in an FPGA, I don't think there is a commercially available FPGA that is capable of this 1GHz operation or the 4GHz operation the OP has been discussing.

I suspect this was posted in the wrong section and should have been posted in the ASIC section. The waveforms shown are probably out of some simulation tool.

I would have moved it but by the time I saw it on Wednesday the post already had a bunch of replies, including by some moderators

Hi ads_ee, this is a kind of mix-signal design - clock dividers associating with an RF design in my circuit. So it is hard to post it in an individual RF section with only pure RF expert's help. Please sympathize with the situation.
P/S: i 've just looked at the section name, it is digital design & embedded stuff. Honestly, i first posted in analog design section, and dont know why it jumped into here. sorry !

 

[FvM]

Honestly, i first posted in analog design section, and dont know why it jumped into here. sorry !

The post was moved by a moderator because clock divider is clearly a digital design topic. The original question didn't give any hints if you are working on custom chip design (ASIC) or are using dedicated or programmable logic IC. I don't think that forum assignment is the problem here, it's rather the unclear specification. In usual terminology, "non-overlapping" involves a delay between consecutive pulses, but no timing details have been yet specified.

It's unclear to me which circuit was used for the simulation in post #17.