[SOLVED] 74HC595 operation problem

[pic.programmer]

@SunnySkyGuy

See this thread

https://www.edaboard.com/threads/343271/

It is the other thread of the OP. He says he doesn't have free pins to use 3 pins for 74HC595.

 

[FvM]

It is the other thread of the OP. He says he doesn't have free pins to use 3 pins for 74HC595.

Yes, and you know that the problem of controlling HC595 with one or two pins has been solved in this thread.

You can use a common shift and latch clock if you don't mind output pulses during data shift. I think it's a bad idea. Or you need low-pass filters for the chattering outputs.

 

[ahsan_i_h]

You are not reloading the buf variable after the first loop.
Moreover, what exactly do you expect with this buf>=1 command ?

Could someone explain what is the purpose of buf>=1. May be it should be buf>>=1.

 

[D.A.(Tony)Stewart]

@SunnySkyGuy

See this thread

https://www.edaboard.com/threads/343271/

It is the other thread of the OP. He says he doesn't have free pins to use 3 pins for 74HC595.

Hmm, I didn't know it was hidden there.

I suppose a 1 wire protocol would work with Short/long pulses for 1,0, Reset, & Latch

Or one could bit bang Biphase Clock and Data with an XOR+RC simple clock and data separator with a long pulse "0" for Load and long "1" for Reset.

I remember not having enough ADC 12bit channels in a high speed synchronous SCADA link I designed in the late 70's to monitor servo motor current in case of a potential stall current from load friction, so I made a Current to Frequency converter and sent all the analog currents as a single bit in a supervisory channel with a few extra bits to spare. then F back to V for some edge mounted panel meters for additional remote console feedback on an automated robotic probe scanner. The frame rate was fast enough to bang these asynchronous frequency that I sync'd to prevent aliasing so that I could send 0~8Khz in a 8KHz frame rate .

 

[Arrowspace]

Instead of SH_CP and ST_CP tied, why not use independent ST_CP ?

Also only 7 ports are needed so it could be done in SH_CP 7 Clk pulses and use only Q0~Q6 and not use Q7.

Then the output ports are synchronously switched every byte instead of shifted every bit, unless that was the desired feature?

I do't get it.

 

[FvM]

May be it should be buf>>=1.

At least, that's the right syntax for an unitary shift operation. buf >=1 does nothing.

 

[Arrowspace]

circuit is correct and working smoothly