tpic6b595
Dear PiCS,
Your 7x40 design is very nice but uses far too many ICs. Have you considered;
(1) Using five 'HC595 / '2003 pairs to drive 40 columns instead of eight pairs?
(2) Using five serial-to-parallel sinking driver ICs instead of 'HC595 / '2003 pairs?
(3) Using five serial-to-parallel constant current sinking driver ICs instead (no current limiting resistors required)?
(4) Modulating the 'HC595 or other drivers mentioned above with PIC PWM signal for full fade-to-black brightness control?
Here's a variation of the design for your consideration. You could still load 40 bits of column data into cascaded driver IC shift registers if you like but you could also take advantage of the PWM signal to multiplex those row driver lines and use them to load the driver IC shift registers in parallel during a small blanking interval at the beginning of each interrupt cycle when the PWM line is high and the displays are off. This allows you to load the shift registers simply by throwing 8 bytes onto the bus with a clock pulse after each byte. Of course you still need to format the 8 special bytes later in the ISR with all of the b7 shift register bits in one byte, b6 shift register bytes in another byte, and so on for the next interrupt cycle, but this takes very little code and time.
Display brightness is inversely proportional to PWM duty cycle and the PWM period must equal the row scan interval. A 100% duty cycle corresponds to 0% brightness (a 'black' display). Use something like a 2% min. duty cycle (98% max. brightness) to allow enough time for a small blanking interval to load the driver IC shift registers at the beginning of each interrupt cycle.
Kind regards,
Mike K8LH