Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

70MHz peak detector/amplitude detector

Status
Not open for further replies.
Hey E-design,

First, I appreciate your help!
I built the circuit on a proto-board with 2 BAT54WT1G (see the pic).
I see that you got a good result, I'll try to see if I did a mistake. Anyway, I'll order it on a PCB.

Second, I tried to connect it to HCMOS clock 66.66 MHz with 3Vpp and get the amplitude, but I get weird results. The Vpp of the peak detector getting (much) bigger. Do you have any idea? (or it is just me ;-) )


BAT54:
https://nl.farnell.com/on-semicondu...categorieën&categoryNameResp=Alle+categorieën

HCMOS:
https://www.farnell.com/datasheets/75480.pdf

 

I would suggest that you construct it with RF in mind. That will be short tight connections with a good ground plane to minimize unwanted stray capacitance and inductance's. Look at this paper and note construction techniques on pg 17.

You used a BAT54S, but the idea was to use the **broken link removed**, which share two devices with a common anode in one package.
 
Hey E-design,

I used the BAT54S because that's what I had. Shouldn't be a problem in the circuit, no?
Thanks for the book. I'm learning....
Can you upload a picture of your board?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top