Relation between PCB trace width and number of layers

[newbie_hs]

I need to design a PCB for RF Application.
The board contains jsut 4 sma connectors .Connected as shown below.

The frequency of operation is 20Ghz. Trace impedance should be 50 Ohm.Current 1A
Initially I decided to use 2layer board.Then I was told to use 4 layer board .The reason was told is it will help to reduce the trace width.

May I know is there any relation between PCB trace width and number of layers

 

[FvM]

You are creating planar, coplanar or embedded transmission lines. Correct trace width for 50 ohm impedance is different for each transmission geometry.

I don't see a general advantage in using multiple layers for RF transmission lines. Assume you achieve highest power rating with basic planar geometry (two layer).

 

[barry]

For microstrip,the impedance is directly related to the distance between a trace and ground plane. In other words, for a given impedance, a thinner pcb will require a thinner trace, but adding layers does nothing.

HOWEVER, if you use stripline, i.e., 3 layers, you can use a thinner width.

Look at this.

 

[D.A.(Tony)Stewart]

A 2 layer microstrip shares air on one side (Dk=1.01 to 1.04 (?) depending on humidity) and a dielectric substrate Dk= X in between the bottom side ground plane. At low f < 1MHz the effective Dk (or er eff.) might be 60% to 70% typ. of the substrate depending which. Meanwhile, when buried between conductors layers or stripline it is 100% of Dk. Microstrip will also radiate more like an antenna patch but not as effective.

Since the microwave skin effect is very sensitive, at 20 GHz the conductor thickness, roughness and material are just as critical as the low-loss tangent dielectric e.g. PTFE, Rogers (e.g. Duroid 5880) or a custom ceramic substrate. This will affect your stripline forward and return loss and vary significantly up to 20 GHz as well as the length if mismatched.

As @barry mentioned using 3 (or 4 layer) allows thinner traces because Dk is now 100%,

Essentially is the ratio of the square root of L/C where L depends on a log of the length/width ratio and C depends on Dk times a ratio of the area per unit length over the gap (Dk*a/g) times some constant for units in metric or not. Thus for a given length, Zo = 50 Ohms can be a thin trace and even thinner with a thinner substrate.
Dielectric tolerances are often 10% so electrical testing is recommended where the Mfg uses a test coupon outside your layout and verifies by TDR or a time-domain reflectometer to your tolerance specs. Copper thickness can also vary the impedance another 10% but this is predictable until you get to 20 GHz then the surface roughness increases the length and inductance per unit length more than the capacitance. Conductor losses are also a factor and some go to the trouble to gold electroplate the traces.

Find out what your tolerance expectations are and how you will verify it.

 

[KlausST]

Then I was told to use 4 layer board .The reason was told is it will help to reduce the trace width.

Why not ask them for explanations? ... or calculation examples?

The 1A current ... is it 1A @ 20GHz, or is it some DC for amplifier supply?

Regarding your sketch:
Be sure to connect the GNDs, too. Either individually for a connector pair, or combined for all connectors ... depending on your application.
I´m rather sure the whole system does not work without the GNDs.

Klaus

 

[newbie_hs]

You are creating planar, coplanar or embedded transmission lines. Correct trace width for 50 ohm impedance is different for each transmission geometry.

I don't see a general advantage in using multiple layers for RF transmission lines. Assume you achieve highest power rating with basic planar geometry (two layer).

I am using a Standard Microstrip (I mean,a single trace on the surface layer of the PCB, with a ground plane directly below it).In the top side also GND pouring will be there.Hope that is not an issue.
If I did the ground pouring on top also will it become a coplanar microstrip

--- Updated Oct 16, 2024 ---

Below is the equation for microstrip Zo provided by @barry .

I can say that Zo is proportional to h/w (Height/width).
So I can rewrite as W is proportional to h/Zo
Zo is fixed here.
So lower the h lower the W
Is my understanding is correct.

 

[marce]

Either a thin board, or if 1.6mm required a 4 layer board, with a FR4 core and outer layers on a rogers laminate. All inner layers 0V's, with stitching vias...

--- Updated Oct 17, 2024 ---

Use Saturn PCB toolkit, it will make life easier for calculating impedances...

 

[newbie_hs]

stitching vias..

May I know the aspect ratio and spacing between vias